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NX25F011B View Datasheet(PDF) - Unspecified

Part NameDescriptionManufacturer
NX25F011B 1M-BIT, 2M-BIT, AND 4M-BIT SERIAL FLASH MEMORIES WITH 4-PIN SPI INTERFACE ETC1
Unspecified 
NX25F011B Datasheet PDF : 37 Pages
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NX25F011B
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NX25F041B
Compare Sector to SRAM (8DH)
The Compare Sector to SRAM command (8DH) does a
bit-by-bit comparison of the data stored in the addressed
sector against data in the SRAM. The TR bit will be 1 during
the transfer compare operation. If any of the compared bits
are not equal, then the Compare Not Equal (CNE) bit in the
Status Register is set to a 1. This bit will stay set until a Clear
1 Compare Status command has been issued. Note that the
Compare Sector to SRAM Clocked command can be used
if partial compares are required. This command is very
useful for performing a fast verify of the Last Sector write
operation. This verify provides for the highest data integrity.
2
Compare Sector
with SRAM Sector
Sector
Command Address* Address* 16 Clocks Compare Time
3
SI
8DH
S[15:0]
B[15:0]
0000H
(tXS)
SO
4
*The sector address only uses bits [8:0], [9:0] or [10:0]
Depending on device density
5
6
CONFIGURATION AND STATUS
COMMANDS
Read Configuration Register (8CH)
The Read Configuration Register command provides
access to the configuration register, which stores the
current configuration of the HOLD-R/B pin, read clock
edge, write protect range, and alternate oscillator
frequency (Figure 7). A 16-bit Configuration Data field
CF[15:0] provides the contents of the Configuration
Register. Although the field is 16-bits long, only bits
CF[7:0] are used. All other upper bits are reserved for
future features.
Read Configuration
Register
Command
SI
8CH
SO
CF{15:0}*
Read Configuration Bits
*The CF Register only uses bits [7:0]
7
8
9
10
11
12
NexFlash Technologies, Inc.
21
PRELIMINARY NXSF016F-1201
12/12/01 ©
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