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NX25F011B View Datasheet(PDF) - Unspecified

Part NameDescriptionManufacturer
NX25F011B 1M-BIT, 2M-BIT, AND 4M-BIT SERIAL FLASH MEMORIES WITH 4-PIN SPI INTERFACE ETC1
Unspecified 
NX25F011B Datasheet PDF : 37 Pages
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NX25F011B
NX25F021B
NX25F041B
Command Set
The NX25F011B, NX25F021B, and NX25F041B have a
powerful command set that is fully controlled through the
SPI bus. Command relations are shown in Figure 5 and a
list of commands and their associated address, status,
clock, and data bytes are shown in Table 3. Detailed clock
timing of the Read Sector and Write Sector command
sequences are shown in Figures 9 and 10.
After power up, a device enters an idle state that will
maintain until CS pin is asserted low. All commands are
entered from the SPI serial data input (SI) pin on the rising
edge of SCK while CS is asserted low. All command,
address, and configuration bits are shifted into the device
with most-significant-bit-first. Data bits read from the
device are shifted out with least significant byte first
(i.e., byte-00H, byte-01H,...). The bit order within each
byte is most-significant-bit first (i.e.,D7,...D0). All com-
mands are completed by asserting the CS pin high.
Note that the entire 264-byte contents of a Flash sector or
the SRAM does not have to be accessed all at once. Read,
Write, Transfer Clocked, and Compare Clocked com-
mands allow for byte addressing. Thus a single byte, or
clocked sequence of bytes, can be accessed at any
starting location within the 264-byte boundary as specified
by the byte-address field.
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
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