ERASE AND PROGRAMMING PERFORMANCE
Sector Erase Time
Chip Erase Time
Byte Programming Time
Chip Programming Time (Note 3)
Typ (Note 1)
Max (Note 2)
sec Excludes 00h programming prior to
sec erasure (Note 4)
µs Excludes system-level overhead
sec (Note 5)
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 6 for further
information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
Input Voltage with respect to VSS on I/O pins
Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.
VCC + 1.0 V
TSOP AND SO PIN CAPACITANCE
Control Pin Capacitance
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Minimum Pattern Data Retention Time
VIN = 0
VOUT = 0
VIN = 0
Min Max Unit