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AM29F016B-150EE View Datasheet(PDF) - Advanced Micro Devices

Part NameDescriptionManufacturer
AM29F016B-150EE 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory AMD
Advanced Micro Devices AMD
AM29F016B-150EE Datasheet PDF : 38 Pages
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PRELIMINARY
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary
Sector Group Unprotect
Completed (Note 2)
Notes:
21444B-8
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
Figure 1. Temporary Sector Group Unprotect
Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during VCC power-up and
power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
= VIL, CE# = VIH or WE# = VIH. To initiate a write cy-
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to reading array data on
power-up.
12
Am29F016B
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