PRELIMINARY
AC CHARACTERISTICS
Addresses
CE#
OE#
WE#
DQ7
tRC
VA
tACC
tCE
tCH
tOEH
tOE
tDF
tOH
Complement
VA
Complement True
VA
Valid Data
High Z
DQ0–DQ6
RY/BY#
tBUSY
Status Data
Status Data
True
Valid Data
High Z
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
21358F-23
Figure 19. Data# Polling Timings (During Embedded Algorithms)
Addresses
CE#
OE#
WE#
DQ6/DQ2
RY/BY#
tRC
VA
tACC
tCE
tCH
tOE
tOEH
tDF
High Z
tBUSY
tOH
Valid Status
(first read)
VA
Valid Status
(second read)
VA
VA
Valid Status
(stops toggling)
Valid Data
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
21358F-24
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
Am29LV160B
37