M50FW016N1G View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M50FW016N1G Datasheet PDF : 45 Pages
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M50FW016
hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is is-
sued, otherwise the new command will appear to
fail.
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended and is waiting to be re-
sumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Control-
ler inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Program Suspend Status bit is ‘0’ the
Program/Erase Controller is active or has complet-
ed its operation; when the bit is ‘1’ a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if the Pro-
gram or Block Erase operation has tried to modify
the contents of a protected block. When the Block
Protection Status bit is to ‘0’ no Program or Block
Erase operations have been attempted to protect-
ed blocks since the last Clear Status Register
command or hardware reset; when the Block Pro-
tection Status bit is ‘1’ a Program or Block Erase
operation has been attempted on a protected
block.
Once it is set to ‘1’ the Block Protection Status bit
can only be reset to ‘0’ by a Clear Status Register
command or a hardware reset. If it is set to ‘1’ it
should be reset before a new Program or Block
Erase command is issued, otherwise the new
command will appear to fail.
Using the A/A Mux Interface the Block Protection
Status bit is always ‘0’.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.
Table 11. Status Register Bits
Operation
Bit 7 Bit 6
Program active
‘0’
X(1)
Program suspended
‘1
X(1)
Program completed successfully
‘1’
X(1)
Program failure due to VPP Error
‘1’
X(1)
Program failure due to Block Protection (FWH Interface only) ‘1’ X(1)
Program failure due to cell failure
‘1’
X(1)
Erase active
‘0’
‘0’
Block Erase suspended
‘1’
‘1’
Erase completed successfully
‘1’
‘0’
Erase failure due to VPP Error
‘1’
‘0’
Block Erase failure due to Block Protection (FWH Interface
only)
‘1’
‘0’
Erase failure due to failed cell(s)
‘1’
‘0’
Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.
Bit 5
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
Bit 4
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Bit 3
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
Bit 2
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Bit 1
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
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