M50FW016N1T View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M50FW016N1T Datasheet PDF : 45 Pages
| |||
M50FW016
STATUS REGISTER
The Status Register provides information on the
current or previous Program or Erase operation.
Different bits in the Status Register convey
different information and errors on the operation.
To read the Status Register the Read Status
Register command can be issued. The Status
Register is automatically read after Program,
Erase and Program/Erase Resume commands
are issued. The Status Register can be read from
any address.
The Status Register bits are summarized in Table
11., Status Register Bits. Refer to Table 11. in
conjunction with the text descriptions below.
Program/Erase Controller Status (Bit 7). The Pro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
‘0’, the Program/Erase Controller is active; when
the bit is ‘1’, the Program/Erase Controller is inac-
tive.
The Program/Erase Controller Status is ‘0’ imme-
diately after a Program/Erase Suspend command
is issued until the Program/Erase Controller paus-
es. After the Program/Erase Controller pauses the
bit is ‘1’.
During Program and Erase operation the Pro-
gram/Erase Controller Status bit can be polled to
find the end of the operation. The other bits in the
Status Register should not be tested until the Pro-
gram/Erase Controller completes the operation
and the bit is ‘1’.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, VPP
Status and Block Protection Status bits should be
tested for errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that a Block Erase oper-
ation has been suspended and is waiting to be
resumed. The Erase Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Control-
ler inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is ‘0’ the Pro-
gram/Erase Controller is active or has completed
its operation; when the bit is ‘1’ a Program/Erase
Suspend command has been issued and the
memory is waiting for a Program/Erase Resume
command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns to ‘0’.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has applied the
maximum number of erase pulses to the block(s)
and still failed to verify that the block(s) has erased
correctly. The Erase Status bit should be read
once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Erase Status bit is ‘0’ the memory has
successfully verified that the block(s) has erased
correctly; when the Erase Status bit is ‘1’ the Pro-
gram/Erase Controller has applied the maximum
number of pulses to the block(s) and still failed to
verify that the block(s) has erased correctly.
Once the Erase Status bit is set to ‘1’ it can only be
reset to ‘0’ by a Clear Status Register command or
a hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is is-
sued, otherwise the new command will appear to
fail. (When Bit 4 and Bit 5 are set to ‘1’, a wrong
command sequence has been attempted).
Program Status (Bit 4). The Program Status bit
can be used to identify if the memory has applied
the maximum number of program pulses to the
byte and still failed to verify that the byte has pro-
grammed correctly. The Program Status bit should
be read once the Program/Erase Controller Status
bit is ‘1’ (Program/Erase Controller inactive).
When the Program Status bit is ‘0’ the memory has
successfully verified that the byte has pro-
grammed correctly; when the Program Status bit is
‘1’ the Program/Erase Controller has applied the
maximum number of pulses to the byte and still
failed to verify that the byte has programmed cor-
rectly.
Once the Program Status bit is set to ‘1’ it can only
be reset to ‘0’ by a Clear Status Register com-
mand or a hardware reset. If it is set to ‘1’ it should
be reset before a new Program or Erase command
is issued, otherwise the new command will appear
to fail. (When Bit 4 and Bit 5 are set to ‘1’, a wrong
command sequence has been attempted).
VPP Status (Bit 3). The VPP Status bit can be
used to identify an invalid voltage on the VPP pin
during Program and Erase operations. The VPP
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can oc-
cur if VPP becomes invalid during a Program or
Erase operation.
When the VPP Status bit is ‘0’ the voltage on the
VPP pin was sampled at a valid voltage; when the
VPP Status bit is ‘1’ the VPP pin has a voltage that
is below the VPP Lockout Voltage, VPPLK, the
memory is protected; Program and Erase opera-
tion cannot be performed. (The VPP status bit is ‘1’
if a Quadruple Byte Program command is issued
and the VPP signal has a voltage less than VPPH
applied to it.)
Once the VPP Status bit set to ‘1’ it can only be re-
set to ‘0’ by a Clear Status Register command or a
20/45
|
|
Share Link: 