M28W160BT85GB6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M28W160BT85GB6

16 Mbit (1Mb x16, Boot Block) 3V Supply Flash Memory

STMicroelectronics 

M28W160BT, M28W160BB

commands will be ignored. Typical Program times

are given in Table 6, Program, Erase Times and

Program/Erase Endurance Cycles.

Programming aborts if Reset goes to VIL. As data

integrity cannot be guaranteed when the program

operation is aborted, the block containing the

memory location must be erased and repro-

grammed.

See Appendix C, Figure 20, Program Flowchart

and Pseudo Code, for the flowchart for using the

Program command.

Double Word Program Command

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel.The two words must differ only for the

address A0. Programming should not be attempt-

ed when VPP is not at VPPH. The command can be

executed if VPP is below VPPH but the result is not

guaranteed.

Three bus write cycles are necessary to issue the

Double Word Program command.

s The first bus cycle sets up the Double Word

Program command.

s The second bus cycle latches the Address and

the Data of the first word to be written.

s The third bus cycle latches the Address and the

Data of the second word to be written and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started. Program-

ming aborts if Reset goes to VIL. As data integrity

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See Appendix C, Figure 21, Double Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Double Word Program

command.

Clear Status Register Command

The Clear Status Register command can be used

to reset bits 1, 3, 4 and 5 in the Status Register to

‘0’. One bus write cycle is required to issue the

Clear Status Register command.

The bits in the Status Register do not automatical-

ly return to ‘0’ when a new Program or Erase com-

mand is issued. The error bits in the Status

Register should be cleared before attempting a

new Program or Erase command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to

pause a Program or Erase operation. One bus

write cycle is required to issue the Program/Erase

command and pause the Program/Erase control-

ler.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

Read Array, Read Status Register, Read Electron-

ic Signature and Read CFI Query commands. Ad-

ditionally, if the suspend operation was Erase then

the Program command will also be accepted. Only

the blocks not being erased may be read or pro-

grammed correctly.

During a Program/Erase Suspend, the device can

be placed in a pseudo-standby mode by taking

Chip Enable to VIH. Program/Erase is aborted if

Reset turns to VIL.

See Appendix C, Figure 22, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

24, Erase Suspend & Resume Flowchart and

Pseudo Code for flowcharts for using the Program/

Erase Suspend command.

Program/Erase Resume Command

The Program/Erase Resume command can be

used to restart the Program/Erase Controller after

a Program/Erase Suspend operation has paused

it. One Bus Write cycle is required to issue the

command. Once the command is issued subse-

quent Bus Read operations read the Status Reg-

ister.

See Appendix C, Figure 22, Program or Double

Word Program Suspend & Resume Flowchart and

Pseudo Code, and Figure 24, Erase Suspend &

Resume Flowchart and Pseudo Code for flow-

charts for using the Program/Erase Resume com-

mand.

Block Protection

Two parameter/lockable blocks (blocks #0 and #1)

can be protected against Program or Erase oper-

ations. Unprotected blocks can be programmed or

erased.

To protect the two lockable blocks set Write Pro-

tect to VIL. When VPP is below VPPLK all blocks are

protected. Any attempt to Program or Erase pro-

tected blocks will abort, the data in the block will

not be changed and the Status Register outputs

the error.

Table 5, Memory Blocks Protection Truth Table,

defines the protection methods.

13/45

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