M28W160BT85GB6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M28W160BT85GB6

16 Mbit (1Mb x16, Boot Block) 3V Supply Flash Memory

STMicroelectronics 

M28W160BT, M28W160BB

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

dles all timings and verifies the correct execution

of the Program and Erase commands. The Pro-

gram/Erase Controller provides a Status Register

whose output may be read at any time, to monitor

the progress of an operation, or the Program/

Erase states. See Appendix D, Table 30, Write

State Machine Current/Next, for a summary of the

Command Interface.

The Command Interface is reset to Read mode

when power is first applied, when exiting from Re-

set or whenever VDD is lower than VLKO. Com-

mand sequences must be followed exactly. Any

invalid combination of commands will reset the de-

vice to Read mode. Refer to Table 3, Commands,

in conjunction with the text descriptions below.

Read Memory Array command

The Read command returns the memory to its

Read mode. One Bus Write cycle is required to is-

sue the Read Memory Array command and return

the memory to Read mode. Subsequent read op-

erations will read the addressed location and out-

put the data. When a device Reset occurs, the

memory defaults to Read mode.

Read Status Register Command

The Status Register indicates when a program or

erase operation is complete and the success or

failure of the operation itself. Issue a Read Status

Register command to read the Status Register’s

contents. Subsequent Bus Read operations read

the Status Register, at any address, until another

command is issued. See Table 7, Status Register

Bits, for details on the definitions of the bits.

The Read Status Register command may be is-

sued at any time, even during a Program/Erase

operation. Any Read attempt during a Program/

Erase operation will automatically output the con-

tent of the Status Register.

Read Electronic Signature Command

The Read Electronic Signature command reads

the Manufacturer and Device Codes.

The Read Electronic Signature command consists

of one write cycle, a subsequent read will output

the Manufacturer or the Device Code depending

on the levels of A0. The Manufacturer Code is out-

put when the address line A0 is at VIL, the Device

Code is output when A0 is at VIH. Addresses A1-

A7 must be kept to VIL, other addresses are ig-

nored. The codes are output on DQ0-DQ7 with

DQ8-DQ15 at 00h. (see Table 4)

Read CFI Query Command

The Read Query Command is used to read data

from the Common Flash Interface (CFI) Memory

Area, allowing programming equipment or appli-

cations to automatically match their interface to

the characteristics of the device.

One Bus Write cycle is required to issue the Read

Query Command. Once the command is issued

subsequent Bus Read operations read from the

Common Flash Interface Memory Area. See Ap-

pendix B, Common Flash Interface, Tables 24, 25,

26, 27, 28 and 29 for details on the information

contained in the Common Flash Interface memory

area.

Block Erase Command

The Block Erase command can be used to erase

a block. It sets all the bits within the selected block

to ’1’. All previous data in the block is lost. If the

block is protected then the Erase operation will

abort, the data in the block will not be changed and

the Status Register will output the error.

Two Bus Write cycles are required to issue the

command.

s The first bus cycle sets up the Erase command.

s The second latches the block address in the

internal state machine and starts the Program/

Erase Controller.

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits b4 and b5 are set and

the command aborts.

Erase aborts if Reset turns to VIL. As data integrity

cannot be guaranteed when the Erase operation is

aborted, the block must be erased again.

During Erase operations the memory will only ac-

cept the Read Status Register command and the

Program/Erase Suspend command, all other com-

mands will be ignored. Typical Erase times are

given in Table 6, Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

See Appendix C, Figure 23, Erase Flowchart and

Pseudo Code, for the flowchart for using the Erase

command.

Program Command

The memory array can be programmed word-by-

word. Two bus write cycles are required to issue

the Program command.

s The first bus cycle sets up the Program

command.

s The second latches the Address and the Data to

be written and starts the Program/Erase

Controller.

During Program operations the memory will only

accept the Read Status Register command and

the Program/Erase Suspend command. All other

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