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ST24CM1 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
ST24CM1 16 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST24CM1 Datasheet PDF : 17 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ST24/25C16, ST24/25W16
Table 7. AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
Symbol
Alt
Parameter
Min
Max
Unit
tCH1CH2
tR
Clock Rise Time
1
µs
tCL1CL2
tF
Clock Fall Time
300
ns
tDH1DH2
tR
Input Rise Time
1
µs
tDL1DL1
tCHDX (1)
tF
tSU:STA
Input Fall Time
Clock High to Input Transition
300
ns
4.7
µs
tCHCL
tHIGH
Clock Pulse Width High
4
µs
tDLCL
tHD:STA
Input Low to Clock Low (START)
4
µs
tCLDX
tHD:DAT
Clock Low to Input Transition
0
µs
tCLCH
tLOW
Clock Pulse Width Low
4.7
µs
tDXCX
tSU:DAT
Input Transition to Clock Transition
250
ns
tCHDH
tSU:STO Clock High to Input High (STOP)
4.7
µs
tDHDL
tCLQV (2)
tBUF
Input High to Input Low (Bus Free)
tAA
Clock Low to Next Data Out Valid
4.7
µs
0.3
3.5
µs
tCLQX
tDH
Data Out Hold Time
300
ns
fC
fSCL
Clock Frequency
100
kHz
tW (3)
tWR
Write Time
10
ms
Notes: 1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (5 address MSB are not constant)
the maximum programming time is doubled to 20ms.
Table 8. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref.
Voltages
50ns
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
Figure 4. AC Testing Input Output Waveforms
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI00825
DEVICE OPERATION
I2C Bus Background
The ST24/25x16 support the I2C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x16 are always slave
devices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x16 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
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