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ST24CM1 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
ST24CM1 16 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST24CM1 Datasheet PDF : 17 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ST24/25C16, ST24/25W16
SIGNALS DESCRIPTION
Serial Clock (SCL). The SCL input signal is used
to synchronise all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA signal is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 3).
Protected Block Select (PB0, PB1). PB0 and PB1
input signals select the block in the upper part of
the memory where write protection starts. These
inputs have a CMOS compatible input level.
Protect Enable (PRE). The PRE input signal, in
addition to the status of the Block Address Pointer
bit (b2, location 7FFh as in Figure 7), sets the PRE
write protection active.
Mode (MODE). The MODE input is available on pin
7 (see also WC feature) and may be driven dynami-
cally. It must be at VIL or VIH for the Byte Write
mode, VIH for Multibyte Write mode or VIL for Page
Write mode. When unconnected, the MODE input
is internally read as VIH (Multibyte Write mode).
Write Control (WC). An hardware Write Control
feature is offered only for ST24W16 and ST25W16
versions on pin 7. This feature is usefull to protect
the contents of the memory from any erroneous
erase/write cycle. The Write Control signal is used
to enable (WC at VIH) or disable (WC at VIL) the
internal write protection. When unconnected, the
WC input is internally read as VIL. The devices with
this Write Control feature no longer supports the
Multibyte Write mode of operation, however all
other write modes are fully supported.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
20
VCC
16
12
8
4
VCC = 5V
SDA
MASTER SCL
RL
RL
CBUS
CBUS
0
100
200
300
400
CBUS (pF)
AI01100
4/17
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