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ST24CM1 View Datasheet(PDF) - STMicroelectronics

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Description
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ST24CM1 Datasheet PDF : 17 Pages
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Table 3. Device Select Code
Bit
b7
Device Select
1
Note: The MSB b7 is sent first.
Device Code
b6
b5
0
1
ST24/25C16, ST24/25W16
Memory MSB Addresses
RW
b4
b3
b2
b1
b0
0
A10
A9
A8
RW
Table 4. Operating Modes
Mode
Current Address Read
RW bit
’1’
’0’
Random Address Read
’1’
Sequential Read
’1’
Byte Write
’0’
Multibyte Write
’0’
Page Write
’0’
Note: X = VIH or VIL.
MODE pin
X
X
X
X
VIH
VIL
Bytes
1
1
1 to 2048
1
8
16
Initial Sequence
START, Device Select, RW = ’1’
START, Device Select, RW = ’0’, Address,
reSTART, Device Select, RW = ’1’
As CURRENT or RANDOM Mode
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
memory it responds to the 8 bits received by as-
serting an acknowledge bit during the 9th bit time.
When data is read by the bus master, it acknow-
ledges the receipt of the data bytes in the same
way. Data transfers are terminated with a STOP
condition.
Data in the 4 upper blocks of the memory may be
write protected. The protected area is programma-
ble to start on any 16 byte boundary. The block in
which the protection starts is selected by the input
pins PB0, PB1. Protection is enabled by setting a
Protect Flag bit when the PRE input pin is driven
High.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Untill the VCC
voltage has reached the POR threshold value, the
internal reset is active: all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
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