M48Z12 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
| M48Z12 Datasheet PDF : 0 Pages | |||
Operation modes
M48Z02, M48Z12
Table 4. WRITE mode AC characteristics
Symbol
Parameter(1)
M48Z02/M48Z12
–70
–150
–200
Unit
Min Max Min Max Min Max
tAVAV
tAVWL
tAVEL
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
tDVEH
tWHDX
tEHDX
tWLQZ
tAVWH
WRITE cycle time
Address valid to WRITE enable low
Address valid to chip enable 1 low
WRITE enable pulse width
Chip enable low to chip enable 1 high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
70
150
200
ns
0
0
0
ns
0
0
0
ns
50
90
120
ns
55
90
120
ns
0
10
10
ns
0
10
10
ns
30
40
60
ns
30
40
60
ns
5
5
5
ns
5
5
5
ns
25
50
60
ns
60
120
140
ns
tAVEH
Address valid to chip enable high
60
120
140
ns
tWHQX WRITE enable high to output transition
5
10
10
ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
2.3
Note:
Data retention mode
With valid VCC applied, the M48Z02/12 operates as a conventional BYTEWIDEâ„¢ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “don't care.â€
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48Z02/12 may respond to transient noise spikes on VCC that reach
into the deselect window during the time the device is sampling VCC. Therefore, decoupling
of the power supply lines is recommended.
The power switching circuit connects external VCC to the RAM and disconnects the battery
when VCC rises above VSO. As VCC rises, the battery voltage is checked. If the voltage is
too low, an internal Battery Not OK (BOK) flag will be set. The BOK flag can be checked
after power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is
automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 7
on page 11 illustrates how a BOK check routine could be structured.
For more information on a battery storage life refer to the application note AN1012.
10/22
Doc ID 2420 Rev 9
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