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MAX5420 View Datasheet(PDF) - Maxim Integrated

Part NameDescriptionManufacturer
MAX5420 Digitally Programmable Precision Voltage Divider for PGAs MaximIC
Maxim Integrated MaximIC
MAX5420 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
Digitally Programmable Precision
Voltage Divider for PGAs
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
VSS to GND...............................................................+0.3V to -6V
D0, D1 to GND ...........................................-0.3V to (VDD + 0.3V)
H, L, W, MATCH_ to GND ................(VSS - 0.3V) to (VDD + 0.3V)
Input and Output Latchup Immunity.................................±50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin µMAX (derate 4.1mW/°C above +70°C) .............333mW
10-Pin µMAX (derate 5.6mW/°C above +70°C) ...........444mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V ±5%, VSS = -5V ±5% or VSS = GND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
MAX542_A
±0.025
Divider Ratio Accuracy
MAX542_B
±0.09 %
MAX542_C
±0.5
H-to-L Resistance
Input Resistance at H
Input Resistance at W
RHL (Figure 1)
RH
Ratio = 1
RW
Ratio = 2, 4, 8
VSS = -5V
VSS = 0
15
k
15
k
300
500
8
k
Capacitance at H, L, W,
MATCH_H, MATCH_L
CANALOG
5
pF
Matching Resistor
MAX5421
Ratio = 1
Ratio = 2, 4, 8
VSS = -5V
VSS = 0
300
500
8
k
DYNAMIC PERFORMANCE
Switching Time
VDD = +5V, VSS = -5V, digital input 0 to +3V,
tS
VW settles to 0.02% of final value with 2pF
capacitive load. Circuit of Figure 2.
0.5
µs
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance
VIH
VIL
D1, D0 = VDD or GND
2.4
V
0.8
±1
µA
5
pF
2 _______________________________________________________________________________________
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