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M464S1724DTS-C1H View Datasheet(PDF) - Samsung

Part Name
Description
Manufacturer
M464S1724DTS-C1H Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
M464S1724DTS
PC133/PC100 SODIMM
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Dont care, H=Logic high, L=Logic low)
Command
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP
A11,
A9 ~ A0
Register
Mode register set
H
X
L
L
L
L
X
OP code
Auto refresh
H
H
L
L
L
H
X
X
Entry
L
Refresh
Self
refresh
Exit
L
H
H
H
L
H
X
X
H
X
X
X
Bank active & row addr.
H
X
L
L
H
H
X
V
Row address
Read &
Auto precharge disable
column address
H
Auto precharge enable
X
L
H
L
H
X
V
L
Column
address
H
(A0 ~ A 8)
Write &
Auto precharge disable
column address
H
Auto precharge enable
X
L
H
L
L
X
V
L
Column
address
H
(A0 ~ A 8)
Burst stop
H
X
L
H
H
L
X
X
Precharge
Bank selection
All banks
V
L
H
X
L
L
H
L
X
X
X
H
H
X
X
X
Clock suspend or
active power down
Entry
H
L
X
L
V
V
V
X
Exit
L
H
XX
X
X
X
H
X
X
X
Entry
H
L
X
Precharge power down mode
L
H
H
H
X
H
X
X
X
Exit
L
H
X
L
V
V
V
DQM
H
X
V
X
No operation command
H
X
X
X
H
X
X
X
L
H
H
H
Notes : 1. OP Code : Operand code
A0 ~ A 11 & B A0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA 0 ~ BA1 : Bank select addresses.
If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA 0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA 0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Note
1,2
3
3
3
3
4
4,5
4
4,5
6
7
Rev. 0.1 Sept. 2001
 

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