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M464S1724DTS-C7C View Datasheet(PDF) - Samsung

Part Name
Description
Manufacturer
M464S1724DTS-C7C Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
M464S1724DTS
PC133/PC100 SODIMM
M464S1724DTS-C7C/L7C/C7A/L7A/C1H/L1H/C1L/L1L
Organization : 8Mx64
Composition : 8Mx16 * 8
Used component part # : K4S281632D-TC7C/TL7C/TC75/TL75/TC1H/TL1H/TC1L/TL1L
# of rows in module : 2 Row
# of banks in component : 4 banks
Feature : 1,250mil height & double sided component
Refresh : 4K/64ms
Contents ;
Byte #
Function Described
Function Supported
-7C
-7A
-1H
-1L
-7C
0 # of bytes written into serial memory at module manufacturer
128bytes
1 Total # of bytes of SPD memory device
256bytes (2K-bit)
2 Fundamental memory type
SDRAM
3 # of row address on this assembly
12
4 # of column address on this assembly
9
5 # of module Rows on this assembly
2 row
6 Data width of this assembly
64 bits
7 ...... Data width of this assembly
-
8 Voltage interface standard of this assembly
LVTTL
9 SDRAM cycle time @CAS latency of 3
7.5ns 7.5ns 10ns 10ns 75h
10 SDRAM access time from clock @CAS latency of 3
5.4ns 5.4ns 6ns 6ns 54h
11 DIMM configuraion type
Non parity
12 Refresh rate & type
15.625us, support self refresh
13 Primary SDRAM width
x16
14 Error checking SDRAM width
None
15 Minimum clock delay for back-to-back random column address
tCCD = 1CLK
16 SDRAM device attributes : Burst lengths supported
1, 2, 4, 8 & full page
17 SDRAM device attributes : # of banks on SDRAM device
4 banks
18 SDRAM device attributes : CAS latency
2 & 3 2 & 3 2 & 3 2 & 3 06h
19 SDRAM device attributes : CS latency
0 CLK
20 SDRAM device attributes : Write latency
0 CLK
21 SDRAM module attributes
Non-buffered, non-registered
& redundant addressing
22 SDRAM device attributes : General
23 SDRAM cycle time @CAS latency of 2
24 SDRAM access time from clock @CAS latency of 2
25 SDRAM cycle time @CAS latency of 1
26 SDRAM access time from clock @CAS latency of 1
27 Minimum row precharge time (=tRP)
28 Minimum row active to row active delay (tRRD)
29 Minimum RAS to CAS delay (=t RCD)
30 Minimum activate precharge time (=tRAS)
31 Module Row density
32 Command and address signal input setup time
33 Command and address signal input hold time
34 Data signal input setup time
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
7.5ns 10ns 10ns 12ns 75h
5.4ns 6ns 6ns 7ns 54h
-
-
-
-
00h
-
-
-
-
00h
15ns 20ns 20ns 20ns 0Fh
15ns 15ns 20ns 20ns 0Fh
15ns 20ns 20ns 20ns 0Fh
45ns 45ns 50ns 50ns 2Dh
2 row of 64MB
1.5ns 1.5ns 2ns 2ns 15h
0.8ns 0.8ns 1ns 1ns 08h
1.5ns 1.5ns 2ns 2ns 15h
Hex value
-7A -1H
80h
08h
04h
0Ch
09h
02h
40h
00h
01h
75h A0h
54h 60h
00h
80h
10h
00h
01h
8Fh
04h
06h 06h
01h
01h
00h
0Eh
A0h A0h
60h 60h
00h 00h
00h 00h
14h 14h
0Fh 14h
14h 14h
2Dh 32h
10h
15h 20h
08h 10h
15h 20h
Note
-1L
1
1
A0h
2
60h
2
06h
C0h
2
70h
2
00h
00h
14h
14h
14h
32h
20h
10h
20h
Rev. 0.1 Sept. 2001
 

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