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M1040-13-161.1328 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
Manufacturer
M1040-13-161.1328
ICST
Integrated Circuit Systems ICST
M1040-13-161.1328 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Integrated
Circuit
Systems, Inc.
Power-Up Initialization Function (INIT Pin)
The initialization function provides a short-term override
of the narrow bandwidth mode when the device is
powered up in order to facilitate phase locking.
When INIT is set to logic 1, initialization is enabled. With
NBW set to logic 1 (narrow bandwidth mode), the
initialization function puts the PLL into wide bandwidth
mode until eight consecutive phase detector cycles
occur without a single LOL event. Once the eight valid
PLL locked states have occurred, the PLL bandwidth is
automatically reduced to narrow bandwidth mode.
When INIT is logic 0, the device is forced into wide
bandwidth mode unconditionally.
External Loop Filter
The M1040 requires the use of an external loop filter
components. These are connected to the provided filter
pins (see Figure 5).
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminary Information
Because of the differential signal path design, the
implementation consists of two identical
complementary RC filters as shown in
Figure 5.
RLOOP CLOOP
RPOST
RLOOP CLOOP
RPOST
CPOST
CPOST
OP_IN nOP_IN
49
OP_OUT nOP_OUT nVC VC
85
67
Figure 5: External Loop Filter
PLL bandwidth is affected by the total “M” (feedback
divider) value, loop filter component values, and other
device parameters. See Table 6, Example External
Loop Filter Component Values, below.
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
For guidance on device or loop filter implementa-
tion, contact CMBU (Commercial Business Unit)
Product Applications at (508) 852-5400.
Example External Loop Filter Component Values1
for M1040-yz-155.5200
VCSO Parameters: KVCO = 200kHz/V, RIN = 100k(pin NBW = 0), VCSO Bandwidth = 700kHz.
Device Configuration
Example External Loop Filter Comp. Values Nominal Performance Using These Values
FREF
(MHz)
19.44 2
FVCSO MR_SEL2:0 MDiv NBW
(MHz)
155.52 0 0 0 8 0
RLOOP
6.8k
CLOOP
10µF
RPOST
82k
CPOST
1000pF
PLL Loop
Bandwidth
315Hz
Damping Passband
Factor Peaking (dB)
5.4
0.07
77.76 3 155.52
010 2 0
3.9k10µF
33k1000pF
715Hz
6.2
0.05
77.76 2 155.52
0 1 1 16 0
12k2.2µF 82k1000pF
275Hz
3.1
0.20
155.52 3 155.52
100 1 0
2.7k10µF
47k470pF
980Hz
6.0
0.05
155.52 2 155.52
101 8 0
5.6k4.7µF 82k1000pF
260Hz
3.0
0.20
Table 6: Example External Loop Filter Component Values
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor,
and Passband Peaking. For PLL Simulator software, go to www.icst.com.
Note 2: Optimal for system clock filtering.
Note 3: Optimal for loop timing mode (LOL or Hitless Switching should not be used).
M1040 Datasheet Rev 0.1
8 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400
 

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