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M1040-13-156.8324 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
Manufacturer
M1040-13-156.8324
ICST
Integrated Circuit Systems ICST
M1040-13-156.8324 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Integrated
Circuit
Systems, Inc.
FUNCTIONAL DESCRIPTION
The M1040 is a PLL (Phase Locked Loop) based clock
generator that generates two output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high “Q” SAW delay line provides a low jitter
clock output.
A pin-selected look-up table is used to select the PLL
feedback divider (M Div) and reference divider (R Div)
as shown in Table 3 on pg. 3. The look-up table provides
flexibility in both the overall frequency multiplication
ratio (total PLL ratio) and phase detector frequency.
External loop filter component values influence the PLL
bandwidth, which is used to optimize jitter attenuation
characteristics.
The device features dual differential inputs with two
input selection modes: manual and automatic upon
clock failure. (The differential inputs are internally
configured for easy single-ended operation.)
The M1040 also includes: a Loss of Lock (LOL) indicator,
a reference mux state acknowledge pin (REF_ACK), a
Narrow Bandwidth control input pin (NBW pin), and a
Power-on Initialization (INIT) input (which overrides
NBW=0 to facilitate acquisition of phase lock).
An automatic input reselection feature, or “AutoSwitch”
is also included in the M1040. When the AutoSwitch
mode is enabled, the device will automatically switch to
the other reference clock input when the currently
selected reference clock fails. Reference selection is
non-revertive, meaning that only one reference
reselection will be made each time that AutoSwitch is
re-enabled.
In addition to the AutoSwitch feature, Hitless Switching
and Phase Build-out options can be ordered with the
device. The Hitless Switching and Phase Build-out
options help assure SONET/SDH MTIE and TDEV
compliance during either a manual or automatic input
reference reselection.
Hitless Switching (HS) provides a controlled output
clock phase change during a reference clock
reselection. HS is triggered by a Loss of Lock detection
by the PLL.
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminary Information
Input Reference Clocks
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
Implementation of single-ended input has been facili-
tated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2, with
50kto Vcc and 50kto ground. Figure 4 shows the
input clock structure and how it is used with either
LVCMOS / LVTTL inputs or a DC- coupled LVPECL
clock.
LVCMOS/
LVTTL
LVPECL
VCC
127
82
X
VCC
127
VCC
50k
50k
50k
VCC
50k
50k
MUX
0
1
82
50k
REF_SEL
Figure 4: Input Reference Clocks
Differential Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the 127
and 82resistors) will work for both AC and DC
coupled LVPECL reference clock lines. These provide
the 50load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(DIF_REF0 or DIF_REF1). The inverting reference input pin
(nDIF_REF0 or nDIF_REF1) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or nDEF_REF1) is left floating (not
connected), the input will self-bias at VCC/2.
M1040 Datasheet Rev 0.1
4 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400
 

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