DatasheetQ Logo
Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

M1040-12-167.7097 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
Manufacturer
M1040-12-167.7097
ICST
Integrated Circuit Systems ICST
M1040-12-167.7097 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Integrated
Circuit
Systems, Inc.
DETAILED BLOCK DIAGRAM
M1040
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminary Information
RLOOP CLOOP
OP_IN
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
RPOST
CPOST
CPOST
nOP_OUT nVC VC
External
Loop Filter
Components
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
INIT
LOL
3
MR_SEL2:0
MUX
0
1
0
1
Auto
Ref Sel
R
Divider
PLL
Phase
Detector RIN
R IN
Loop Filter
Amplifier
LOL
Phase
Detector
M Divider
M / R Divider
LUT
P_SEL
Phase
Locked
Loop
(PLL)
SAW Delay Line
Phase
Shifter
VCSO
P Divider
FOUT0
nFOUT0
FOUT1
nFOUT1
Figure 3: Detailed Block Diagram
PLL DIVIDER SELECTION TABLES
M and R Divider Look-Up Tables (LUT)
The MR_SEL2:0 pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up is defined in
Table 3.
M1040 M/R Divider LUT
Total
MR_SEL3:0 M Div R Div PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
000
81
8
19.44
19.44
0 0 1 64 8
8
19.44
2.43
010
21
2
77.76
77.76
0 1 1 16 8
2
77.76
9.72
100
11
1
155.52
155.52
101
110
88
1
Test Mode1 N/A
155.52
N/A
19.44
N/A
111
2 8 0.25
622.08
77.76
Table 3: M1040 M/R Divider LUT
Note 1: Factory test mode; do not use.
Table 3 provides example Fin and phase detector
frequencies with 155.52MHz VCSO devices
(e.g., M1040-11-155.5200). See “Ordering Information”
on pg. 12.
General Guidelines for M and R Divider Selection
General guidelines for M/R divider selection (see
following pages for more detail):
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is 19.44MHz. The LOL pin should
not be used during loop timing mode.
When LOL is to be used for system health monitoring,
the phase detector frequency should be 5MHz or
greater. Low phase detector frequencies make LOL
overly sensitive, and higher phase detector
frequencies make LOL less sensitive.
The preceding guideline also applies when using the
AutoSwitch Mode, since AutoSwitch uses the LOL
output for clock fault detection.
Post-PLL Divider
The M1040 also features a post-PLL (P) divider for the
output clocks. It divides the VCSO frequency to produce
one of two selectable output frequencies (1/2 or 1/1 of
the VCSO frequency). That selected frequency appears
on both clock output pairs. The P_SEL pin selects the
value for the P divider.
P_SEL
M1040-11-155.52
P Value Output Frequency
(MHz)
1
2
77.76
0
1
155.52
Table 4: P Divider Selector Values and Frequencies
M1040 Datasheet Rev 0.1
3 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400
 

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]