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M1040-11I167.3280 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
Manufacturer
M1040-11I167.3280
ICST
Integrated Circuit Systems ICST
M1040-11I167.3280 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Integrated
Circuit
Systems, Inc.
PIN DESCRIPTIONS
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminary Information
Number
Name
1, 2, 3, 10, 14, 26 GND
I/O
Ground
Configuration
Description
Power supply ground connections.
4
OP_IN
9
nOP_IN
Input
5
8
nOP_OUT
OP_OUT
Output
6
nVC
7
VC
Input
External loop filter connections. See Figure 5,
External Loop Filter, on pg. 8.
11, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
12
FOUT1
13
nFOUT1
15
FOUT0
16
nFOUT0
17
INIT
Output
Output
Input
No internal terminator
Clock output pair 1. Differential LVPECL.
No internal terminator
Internal pull-UP resistor1
Clock output pair 0. Differential LVPECL.
Power-on Initialization; LVCMOS/LVTTL:
Logic 1 allows device to enter narrow mode if
selected (in addition must have 8 LOL=0 counts)
Logic 0 forced device into wide bandwidth mode.
18
P_SEL
Internal pull-down1
Post-PLL , P divider selection. LVCMOS/LVTTL.
See Table 4, P Divider Selector Values
and Frequencies, on pg. 3.
20
nDIF_REF1
Biased to Vcc/2 2
Reference Differential LVPECL/ LVDS
Input
clock input Differential LVPECL/ LVDS, or single
21
DIF_REF1
Internal pull-down resistor1 pair 1.
ended LVCMOS/ LVTTL
22
REF_SEL
Input
Internal pull-down resistor1
Reference clock input selection. LVCMOS/LVTTL.
Logic 1 selects DIF_REF1/nDIF_REF1 inputs
Logic 0 selects DIF_REF0/nDIF_REF0 inputs
23
nDIF_REF0
Biased to Vcc/2 3
Reference Differential LVPECL/ LVDS
24
DIF_REF0
Input
clock input Differential LVPECL/ LVDS, or single
Internal pull-down resistor1 pair 0.
ended LVCMOS/ LVTTL
25
AUTO
Automatic/manual reselection mode for clock input:
Input
Internal pull-down resistor1
Logic 1 automatic reselection upon clock failure
(non-revertive)
Logic 0 manual selection only (using REF_SEL)
27
MR_SEL2
28
MR_SEL1
29
MR_SEL0
M and R divider value selection. LVCMOS/ LVTTL.
Input Internal pull-UP resistor1 See Table 3, M and R Divider Look-Up Tables (LUT)
on pg. 3.
Reference Acknowledgement pin for input mux state;
30
REF_ACK
Output
outputs the currently selected reference input pair:
Logic 1 indicates nDIF_REF1, DIF_REF1
Logic 0 indicates nDIF_REF0, DIF_REF0
31
LOL
Output
Loss of Lock indicator output. 4
Logic 1 indicates loss of lock.
Logic 0 indicates locked condition.
32
NBW
Narrow Bandwidth enable. LVCMOS/LVTTL:
Input Internal pull-UP resistor1 Logic 1 - Narrow loop bandwidth, RIN = 2100k.
Logic 0 - Wide bandwidth, RIN = 100k.
34, 35, 36
DNC
Do Not Connect.
Table 2: Pin Descriptions
Note 1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 10.
Note 2: Biased to Vcc/2, with 50kto Vcc and 50kto ground. Float if using DIF_REF1 as LVCMOS input. See DC Characteristics on pg. 10.
Note 3: Biased to Vcc/2, with 50kto Vcc and 50kto ground. Float if using DIF_REF0 as LVCMOS input. See DC Characteristics on pg. 10.
Note 4: See LVCMOS Outputs in DC Characteristics on pg. 10.
M1040 Datasheet Rev 0.1
2 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400
 

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