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62256 Просмотр технического описания (PDF) - Samsung

Номер в каталогеКомпоненты Описаниепроизводитель
62256 32Kx8 bit Low Power CMOS Static RAM Samsung
Samsung Samsung
62256 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
KM62256C Family
TIMING WAVEFORM OF WRITE CYCLE(1()WE Controlled)
PRELIMINARY
CMOS SRAM
Address
CS
WE
Data in
tAS(3)
tWC
tCW(2)
tAW
tWP(1)
tWR(4)
tDW
tDH
Data Valid
tWHZ
tOW
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2()CS Controlled)
Address
tAS(3)
CS
WE
tWC
tCW(2)
tAW
tWP(1)
tWR(4)
Data in
tDW
tDH
Data Valid
Data out
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins at the latest transition among CS goes low and WE going low : A write end
at the earliest transition among CS going high and WE going high, tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
Revision 3.0
April 1996
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