KM416C254D View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

KM416C254D

256K x 16Bit CMOS Dynamic RAM with Extended Data Out

Samsung 

KM416C254D, KM416V254D

CMOS DRAM

13. tASC, tCAH are referenced to the earlier CAS rising edge.

14. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.

15. tCWD is referenced to the later CAS falling edge at word red-modify-write cycle.

16. tCWL is specified from W falling edge to the earlier CAS rising edge.

17. tCSR is referenced to earlier CAS falling low before RAS transition low.

18. tCHR is referenced to the later CAS rising high after RAS transition low.

RAS

LCAS

UCAS

tCSR

19. tDS, tDH are specified for the earlier CAS falling low.

tCHR

LCAS

UCAS

DQ0 ~ DQ15

W

tDS

tDH

Din

20. f tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.

21. For RAS-only refresh and burst CAS-before-RAS refresh mode, 512(512K) cycle of burst refresh must be executed within 8ms

before and after self refresh, in order to meet refresh specification.

22. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately

before and after self refresh in order to meet refresh specification.

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