IS62WV102416ALL View Datasheet(PDF) - Integrated Silicon Solution

Part Name

Description

Manufacturer

IS62WV102416ALL

1M x 16 HIGH-SPEED LOW POWER ASYNCHRONOUS CMOS STATIC RAM

Integrated Silicon Solution 

IS62WV102416ALL

IS62WV102416BLL

IS65WV102416BLL

1M x 16 HIGH-SPEED LOW POWER

ASYNCHRONOUS CMOS STATIC RAM

JANUARY 2008

FEATURES

• High-speed access times:

25, 35 ns

• High-performance, low-power CMOS process

• Multiple center power and ground pins for greater

noise immunity

• Easy memory expansion with CS1 and OE

options

• CS1 power-down

• Fully static operation: no clock or refresh

required

• TTL compatible inputs and outputs

• Single power supply

VDD 1.65V to 2.2V (IS62WV102416ALL)

speed = 35ns for VDD 1.65V to 2.2V

VDD 2.4V to 3.6V (IS62/65WV102416BLL)

speed = 25ns for VDD 2.4V to 3.6V

• Packages available:

– 48-ball miniBGA (9mm x 11mm)

– 48-pin TSOP (Type I)

• Industrial and Automotive Temperature Support

• Lead-free available

• Data control for upper and lower bytes

DESCRIPTION

The ISSI IS62WV102416ALL/BLL and IS65WV102416BLL

are high-speed, 16M-bit static RAMs organized as 1024K

words by 16 bits. It is fabricated using ISSI's high-perform-

ance CMOS technology. This highly reliable process coupled

with innovative circuit design techniques, yields high-

performance and low power consumption devices.

When CS1 is HIGH (deselected) or when CS2 is LOW

(deselected) or when CS1 is LOW, CS2 is HIGH and both

LB and UB are HIGH, the device assumes a standby mode

at which the power dissipation can be reduced down with

CMOS input levels.

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs. The active LOW Write Enable

(WE) controls both writing and reading of the memory. A

data byte allows Upper Byte (UB) and Lower Byte (LB)

access.

The device is packaged in the JEDEC standard 48-pin

TSOP Type I and 48-pin Mini BGA (9mm x 11mm).

FUNCTIONAL BLOCK DIAGRAM

A0-A19

DECODER

1024K x 16

MEMORY ARRAY

VDD

GND

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

I/O

DATA

CIRCUIT

COLUMN I/O

CS1

OE

WE

UB

LB

CONTROL

CIRCUIT

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com

1

Rev. A

01/18/08

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