IC61LV12816-10K View Datasheet(PDF) - Integrated Circuit Solution Inc

Part Name

Description

Manufacturer

IC61LV12816-10K

128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

Integrated Circuit Solution Inc 

IC61LV12816

WRITE CYCLE NO. 4 (1,3)(LB, UB Controlled, Back-to-Back Write)

t WC

t WC

1

ADDRESS

ADDRESS 1

ADDRESS 2

OE

2

t SA

CE LOW

t HA

t HA

3

WE

t SA

UB, LB

t PWB

WORD 1

t PWB

WORD 2

4

t HZWE

t LZWE

DOUT DATA UNDEFINED

HIGH-Z

t HD

t HD

5

t SD

t SD

DIN

DATAIN

VALID

DATAIN

VALID

6

Notes:

1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be

in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is

referenced to the rising or falling edge of the signal that terminates the Write.

2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.

7

3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.

8

9

10

11

12

Integrated Circuit Solution, Inc.

11

AHSR024-0B 04/23/2004

Share Link: