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HI-8282C View Datasheet(PDF) - Unspecified

Part NameDescriptionManufacturer
HI-8282C ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER Unspecified
Unspecified 
HI-8282C Datasheet PDF : 13 Pages
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HI-8282
FUNCTIONAL DESCRIPTION (cont.)
REPEATER OPERATION
he repeater mode of operation allows a data word that has been
received by the HI-8282 to be placed directly into its FIFO for
transmission. After a 32-bit word has been shifted into Tthe
receiver shift register, the D/R flag will go low. A logic "0" is placed
on the SEL line and EN is strobed. This is the same procedure as
for normal receiver operation and it places the lower byte (16) of the
data word on the data bus. By strobing PL1 at the same time as EN,
now ready to be transmitted according to the parity programmed
into the control word register.
In normal operation, either byte of a received data word may be
read from the receiver latches first by use of SEL input. During
repeater operation however, the lower byte of the data word must
be read first. This is necessary because, as the data is being
read, it is also being loaded into the FIFO and the transmitter
FIFO is always loaded with the lower byte of the data word first.
MASTER RESET (MR)
the byte will also be placed into the transmitter FIFO. SEL is then
taken high and EN is strobed again to place the upper byte of the
data word on the data bus. By strobing PL2 at the same time as EN,
the second byte will also be placed into the FIFO. The data word is
On a Master Reset data transmission and reception are
immediately terminated, all three FIFOs are cleared as are the
FIFO flags at the device pins and in the Status Register. The
Control Register is not affected by a Master Reset.
TIMING DIAGRAMS
429DO
429DO
DATA RATE - EXAMPLE PATTERN
ARINC BIT
DATA
NULL
BIT 30
DATA
NULL
BIT 31
DATA
NULL
BIT 32
WORD GAP
DATA BUS
CWSTR
LOADING CONTROL WORD
VALID
tCWSET
tCWHLD
tCWSTR
BIT 1
NEXT WORD
ARINC DATA
BIT 31
DATA READY FLAG D/R
BYTE SELECT SEL
ENABLE BYTE ON BUS EN
DATA BUS
BIT 32
RECEIVER OPERATON
tD/R
DON'T CARE
tSELEN
tD/REN
tENDATA
tENSEL
DON'T CARE
tEND/R
tEN
tSELEN
DON'T CARE
tENSEL
BYTE 1 VALID
tENEN
tDATAEN
tENDATA
BYTE 2 VALID
tDATAEN
HOLT INTEGRATED CIRCUITS
6
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