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MAQ3693NS View Datasheet(PDF) - Dynex Semiconductor

Part NameDescriptionManufacturer
MAQ3693NS 1553B Bus Controller/Remote Terminal Dynex
Dynex Semiconductor Dynex
MAQ3693NS Datasheet PDF : 41 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Replaces June 1999 version, DS3587-4.0
MA3M6A93609/01/1//33
1553B Bus Controller/Remote Terminal
DS3587-5.0 January 2000
The MA3690/1 chip set has three modes of operation:
remote terminal, bus controller, and passive monitor It has a
dual bus capability, requires minimum support hardware /
software and is implemented on a radiation hard, CMOS/SOS
process. For applications requiring access to Terminal Flag, a
48-Pin DIL MA3693 is available as an alternative to the
MA3690.
As a remote terminal, the MA3690/1 is fully compatible with
Mil-Std-1553B. The chip set obtained SEAFAC approval in
December 1987. All options and mode commands specified by
the Mil Std are implemented Full and meaningful use is made
of status word bits and a comprehensive bit word is provided.
A unique mechanism has been incorporated that allows
the subsystem to declare illegal commands legal, and vice
versa, before the chip set services the command. It should be
noted that use of this mechanism is optional and that the
system defaults to normal operation if the option is not
required. The chip set is easily interfaced to subsystem
memory and is sufficiently flexible to ensure compatibility with
a wide range of microprocessors.
As a bus controller the MA3690/1 has the ability to initiate
all types of 1553B transfer on either of the two buses An
instruction word is set up by the subsystem, prior to
transmission, which contains details of transfer type and bus
selection. Four bits of the instruction word have been used to
specify the conditions under which the chip set will generate a
subsystem interrupt. The most significant bits of the instruction
word have been used to specify the conditions under which the
chip set will perform an automatic retry and the number of
retries to be carried out (max. 3). At the end of each instruction
execution cycle, the chip set writes a report word into the
subsystem memory; the contents of which give the subsystem
an indication of the degree of success of the transfer.
The bus controller may be used in either of two
configurations, i.e. single shot or table driven.
In the single shot configuration, the controller is under
direct control from the subsystem (processor). In table driven
configuration, the controller is given greater autonomy to
execute a table of instructions held in either ROM or RAM.
As a passive monitor, the chip set will monitor all bus
activity and pass any associated information to the subsystem.
As the name implies, in this mode of operation, the chip set is
truly passive and will not reply to command instructions.
FEATURES
s Radiation Hard to 1MRads (Si)
s High SEU Immunity, Latch-Up Free
s CMOS-SOS Technology
s All Inputs and Outputs Fully TTL or CMOS Compatible
s Military Temperature Range -55 to +125°C
s Dual Bus Capability
s Minimal Subsystem Interface
s Powerful Bus Control Facility
s Complete Remote Terminal Protocol
s SEAFAC Approved
SIGNAL DESCRIPTIONS
All signals are TTL compatible unless stated otherwise. An
‘N’ at the end of the signal name denotes an active low signal.
SUPPLIES
VDD
5 volts positive supply
VSS
Ground
CLOCK INPUTS
CK12
12MHz clock
BUS INTERFACE LINES
PDIN0
Input
Positive threshold exceeded on bus 0.
NDIN0
Input
Negative threshold exceeded on bus 0.
TXEN0N Output
Transmit enable for driver on bus 0.
PDOUT0N Output
Positive Manchester data for driver on bus 0.
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