E28F004B5T80 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

E28F004B5T80

SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT

Intel 

SMART 5 BOOT BLOCK MEMORY FAMILY

E

AA1165

1

2

A14

3

A13

4

A12

5

A11

6

A9

7

A8

8

WE#

9

RP#

10

VPP

11

WP#

12

AA178

13

14

A6

15

A5

16

A4

17

A3

18

A2

19

A1

20

28F004B5

Boot Block

40-Lead TSOP

10 mmx 20 mm

TOP VIEW

40

A17

39

GND

38

NC

37

NC

36

A10

35

DQ7

34

DQ6

33

DQ5

32

DQ4

31

VCC

30

VCC

29

NC

28

DQ3

27

DQ2

26

DQ1

25

DQ0

24

OE#

23

GND

22

CE#

21

A0

Figure 3. 40-Lead TSOP Pinout Diagram (Available in 4-Mbit Only)

2.3 Memory Blocking Organization

The boot block product family features an

asymmetrically-blocked architecture providing

system memory integration. Each erase block can

be erased independently of the others up to

100,000 times for commercial temperature or up to

10,000 times for extended temperature. The block

sizes have been chosen to optimize their

functionality for common applications of nonvolatile

storage. The combination of block sizes in the boot

block architecture allow the integration of several

memories into a single chip. For the address

locations of the blocks, see the memory maps in

Figures 4, 5, 6 and 7.

2.3.2

TWO 8-KB PARAMETER BLOCKS

Each boot block component contains two parameter

blocks of 8 Kbytes (8,192 bytes) each to facilitate

storage of frequently updated small parameters that

would normally require an EEPROM. By using

software techniques, the byte-rewrite functionality

of EEPROMs can be emulated. These techniques

are detailed in Intel’s application note, AP-604

Using Intel’s Boot Block Flash Memory Parameter

Blocks to Replace EEPROM. The parameter blocks

are not write-protectable.

2.3.3

MAIN BLOCKS - ONE 96-KB +

ADDITIONAL 128-KB BLOCKS

2.3.1

ONE 16-KB BOOT BLOCK

The boot block is intended to replace a dedicated

boot PROM in a microprocessor or microcontroller-

based system. The 16-Kbyte (16,384 bytes) boot

block is located at either the top (denoted by -T

suffix) or the bottom (-B suffix) of the address map

to accommodate different microprocessor protocols

for boot code location. This boot block features

hardware controllable write-protection to protect the

crucial microprocessor boot code from accidental

modification. The protection of the boot block is

controlled using a combination of the VPP, RP#, and

WP# pins, as is detailed in Section 3.3.

After the allocation of address space to the boot

and parameter blocks, the remainder is divided into

main blocks for data or code storage. Each device

contains one 96-Kbyte (98,304 byte) block and

additional 128-Kbyte (131,072 byte) blocks. The

2-Mbit has one 128-KB block; the 4-Mbit, three; and

the 8-Mbit, seven.

10

ADVANCE INFORMATION

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