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CXD3068Q View Datasheet(PDF) - Sony Semiconductor

Part Name
Description
Manufacturer
CXD3068Q Datasheet PDF : 134 Pages
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CXD3068Q
CD Digital Signal Processor with Built-in Digital Servo Preliminary
Description
The CXD3068Q is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo.
Features
All digital signal processings during playback are
performed with a single chip
Highly integrated mounting possible due to a built-
in RAM
Digital Signal Processor (DSP) Block
Playback mode supporting CAV (Constant Angular
Velocity)
Frame jitter free
0.5× to 4× continuous playback possible
Allows relative rotational velocity readout
Wide capture range playback mode
Spindle rotational velocity following method
Supports 1× to 4× playback variable pitch
playback
Bit clock, which strobes the EFM signal, is
generated by the digital PLL.
EFM data demodulation
Enhanced EFM frame sync signal protection
Refined super strategy-based powerful error
correction
C1: double correction, C2: quadruple correction
Supported during 4× playback
Noise reduction during track jumps
Auto zero-cross mute
Subcode demodulation and Sub-Q data error
detection
Digital spindle servo
16-bit traverse counter
Asymmetry correction circuit
CPU interface on serial bus
Error correction monitor signal, etc. output from a
new CPU interface
Servo auto sequencer
Fine search performs track jumps with high
accuracy
Digital audio interface output
Digital level meter, peak meter
Bilingual supported
VCO control mode
CD TEXT data demodulation
EFM playability reinforcement function
Digital Servo (DSSP) Block
Microcomputer software-based flexible servo control
Offset cancel function for servo error signal
Auto gain control function for servo loop
E:F balance, focus bias adjustment function
Surf jump function supporting micro two-axis
Tracking filter: 6 stages
Focus filter: 5 stages
80 pin QFP (Plastic)
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
Supply voltage
VDD
–0.5 to +4.6 V
Input voltage
VI
–0.5 to +4.6 V
(VSS – 0.5V to VDD + 0.5V)
Output voltage
VO
–0.5 to +4.6 V
(VSS – 0.5V to VDD + 0.5V)
Storage temperature Tstg
–55 to +150 °C
Supply voltage difference
VSS – AVSS –0.3 to +0.3 V
VDD – AVDD –0.3 to +0.3 V
Note) AVDD includes XVDD and AVSS includes XVSS.
Recommended Operating Conditions
Supply voltage
VDD
2.7 to 3.6
V
Operating temperature
Topr
–20 to +75 °C
Input/Output Capacitance
Input pin
CI
9 (Max.)
pF
Output pin
CO
11 (Max.) pF
I/O pin
CI/O
11 (Max.) pF
Note) Measurement conditions VDD = VI = 0V
fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
PE00326-PS
 

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