CAT28F512TA-15T View Datasheet(PDF) - Catalyst Semiconductor => Onsemi
Part Name
Description
Manufacturer
CAT28F512TA-15T Datasheet PDF : 15 Pages
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CAT28F512
Figure 5. Chip Erase Algorithm(1)
START ERASURE
APPLY VPPH
PROGRAM ALL
BYTES TO 00H
INITIALIZE
ADDRESS
INITIALIZE
PLSCNT = 0
WRITE ERASE
SETUP COMMAND
WRITE ERASE
COMMAND
TIME OUT 10ms
WRITE ERASE
VERIFY COMMAND
INCREMENT
ADDRESS
TIME OUT 6µs
READ DATA
FROM DEVICE
DATA =
NO
FFH?
YES
NO
LAST
ADDRESS?
YES
WRITE READ
COMMAND
NO
INC PLSCNT
= 310000 ?
YES
APPLY VPPL
APPLY VPPL
ERASURE
COMPLETED
ERASE
ERROR
BUS
OPERATION COMMAND
COMMENTS
STANDBY
VPP RAMPS TO VPPH
(OR VPP HARDWIRED)
ALL BYTES SHALL BE
PROGRAMMED TO 00
BEFORE AN ERASE
OPERATION
INITIALIZE ADDRESS
PLSCNT = PULSE COUNT
WRITE
ERASE
ACTUAL ERASE
NEEDDAST1A0m=s2P0UHLSE,
DATA = 20H
WRITE
ERASE
DATA = 20H
WAIT
WRITE
ERASE
VERIFY
ADDRESS = BYTE TO VERIFY
DATA = 24A000HHH;;
STOPS ERASE OPERATION
WAIT
READ
READ BYTE TO
VERIFY ERASURE
STANDBY
COMPARE OUTPUT TO FF
INCREMENT PULSE COUNT
WRITE
READ
STANDBY
DATA = 00H
RESETS THE REGISTER
FOR READ OPERATION
VPP RAMPS TO VPPL
(OR VPP HARDWIRED)
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
Doc. No. 1084, Rev. H
10
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