CD40174BC View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
CD40174BC Datasheet PDF : 7 Pages
| |||
AC Electrical Characteristics (Note 5)
TA = 25°C, CL = 50 pF, RL = 200k and tr = tf = 20 ns, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tPHL, tPLH
tPHL
tPLH
tSU
tH
tTHL, tTLH
tWH, tWL
tWL
tRCL
tfCL
fCL
CIN
Propagation Delay Time to a
Logical “0” or Logical “1” from
Clock to Q or Q (CD40175 Only)
Propagation Delay Time to a
Logical “0” from Clear to Q
Propagation Delay Time to a Logical
“1” from Clear to Q (CD40175 Only)
Time Prior to Clock Pulse that
Data must be Present
Time after Clock Pulse that
Data Must be Held
Transition Time
Minimum Clock Pulse Width
Minimum Clear Pulse Width
Maximum Clock Rise Time
Maximum Clock Fall Time
Maximum Clock Frequency
Input Capacitance
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Clear Input
Other Input
190
300
75
110
60
90
180
300
70
110
60
90
230
400
90
150
75
120
45
100
15
40
13
35
−11
0
−4
0
−3
0
100
200
50
100
40
80
130
250
45
100
40
80
120
250
45
100
40
80
15
5.0
5.0
15
50
5.0
50
5.0
50
2.0
3.5
5.0
10
6.0
12
10
15
5.0
7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
MHz
MHz
MHz
pF
pF
CPD
Power Dissipation
Per Package (Note 6)
Note 5: AC Parameters are guaranteed by DC correlated testing.
130
pF
Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application
note, AN-90.
www.fairchildsemi.com
4
|
|
Share Link: 