ERASE AND PROGRAMMING PERFORMANCE
Sector Erase Time
Chip Erase Time
Byte Programming Time
Chip Programming Time (Note 3)
Typ (Note 1)
Max (Note 2)
Excludes 00h programming
prior to erasure (Note 4)
Excludes system level
overhead (Note 5)
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four- or two-bus-cycle sequence for the program command. See
Table 9 for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles per sector.
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
Input voltage with respect to VSS on all I/O pins
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
VCC + 1.0 V
TSOP PIN CAPACITANCE
Control Pin Capacitance
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
VIN = 0
VOUT = 0
VIN = 0
Typ Max Unit
Minimum Pattern Data Retention Time