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ACE1101BX 데이터 시트보기 (PDF) - Fairchild Semiconductor

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ACE1101BX Arithmetic Controller Engine (ACEx™) for Low Power Applications Fairchild
Fairchild Semiconductor Fairchild
ACE1101BX Datasheet PDF : 33 Pages
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5.3 Mode 2: External Event Counter Mode
The external event counter mode is similar to the PWM mode,
except that instead of counting instruction clock pulses, the timer
counts transitions received on the T1 pin (configured as an input).
The T1 pin should be connected to an external device that
generates a pulse for each event to be counted. The input signal
on T1 must have a pulse width equal to or greater than one
instruction cycle.
The timer can be configured to sense either positive-going or
negative-going transitions on the T1 pin. The maximum frequency
at which transitions can be sensed is one-half the frequency of the
instruction clock.
As with the PWM mode, when an underflow occurs, the timer
register is reloaded from the T1RA registers, and counting pro-
ceeds downward from the loaded value.
A block diagram of the timer operating in the external event
counter mode is shown in Figure 16.
The following steps can be used to operate the timer in the
external event counter mode.
1. Configure the T1 pin as an input by clearing bit 2 of PORTGC.
2. Load the initial count into the timer register and the T1RA
register. When this number of external events is detected, the
counter will reach zero, however, it will not underflow until the
next event is detected. To count N pulses, load the value N-1
into the registers. If it is only necessary to count the number of
occurrences and no action needs to be taken at a particular
count, load the value 0xFFFF into the registers.
3. In order to generate an interrupt each time the timer
underflows, clear the T1PND pending flag and then enable
the interrupt by setting the T1EN bit. The G bit must also be
set.
4. Write the appropriate value to the timer control bits T1C3-
T1C2- T1C1 to select the external event counter mode, and
to select the type of transition to be sensed on the T1 pin
(positive-going or negative-going; see Table 11).
5. Set the T1C0 bit register to start the timer.
If interrupts are being used, the Timer1 interrupt service routine
must clear the T1PND flag and take whatever action is required
when the timer underflows. If the user wishes to merely count the
number of occurrences of an event, and anticipates that the
number of events may exceed 65,536, the interrupt service
routine should record the number of underflows by incrementing
a counter in memory. On each underflow, the timer (counter)
register is reloaded with the value from the T1RA register.
Figure 16: External Event Counter Mode
Timer
Underflow
Interrupts
T1
16-bit Autoreload
Register T1RA
BUS
16-bit Timer (Counter)
Edge Selector
Logic
ACE1101 Rev. C.8
23
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