Accumulator A is general-purpose 8-bit register that holds oper-
ands and results of arithmetic calculations or data manipulations.
The Z bit is set if the result of an arithmetic, logic, or data
manipulation operation is zero. Otherwise, the Z bit is cleared.
4.1.2 X Pointer
The X register provides an 11-bit indexing value that can be added
to an 8-bit offset provided in an instruction to create an effective
address. The X register can also be used as a counter or as a
temporary storage register.
4.1.3 Program Counter (PC)
The program counter, a 10-bit register, contains the address of the
next instruction to be executed. After reset, the program counter
is initialized to 0xC00 in normal mode.
4.1.4 Stack Pointer (SP)
The ACE1101 has an automatic program stack. This stack can be
initialized to any location between addresses 0x30-0x3F. By
default, the stack is initialized to 0x3F. Normally, the SP is
initialized by one of the first instructions in an application program.
The stack is configured as a data structure that decrements from
high memory to low memory. Each time a new address is pushed
onto the stack, the SP is decremented by two. Each time an
address is pulled from the stack, the SP is incremented by two. At
any given time, the SP points to the next free location in the stack.
When a subroutine is called by a jump to subroutine (JSR), the
address of the instruction, after the JSR instruction, is automati-
cally pushed onto the stack least significant byte first. When the
subroutine is finished, a return from subroutine (RET) instruction
is executed. The RET pulls the previously stacked return address
from the stack, and loads it into the program counter. Execution
then continues at this recovered return address.
4.1.5 Status Register (SR)
This 8-bit register contains four condition code indicators (C, H, Z,
and N), one interrupt masking bit (G), and an EEPROM write flag
(R). In the ACE1101, condition codes are automatically updated
by most instructions.
The C bit is set if the arithmetic logic unit (ALU) performs a carry
or borrow during an arithmetic operation. The rotate instruction
operates with and through the carry bit to facilitate multiple-word
shift operations. The LDC and INVC instructions facilitate direct bit
manipulation using the carry flag.
Half Carry (H)
The half carry flag indicates whether an overflow has taken place
on the boundary between the two nibbles in the accumulator. It is
primarily used for BCD arithmetic calculation.
The N bit is set if the result of an arithmetic, logic, or data manipulation
operation is negative (MSB = 1). Otherwise, the N bit is cleared. A
result is said to be negative if its most significant bit (MSB) is a one.
Interrupt Mask (G)
The interrupt request mask (G) is a global mask that disables all
maskable interrupt sources. Until the G bit is set, interrupts can become
pending, but the operation of the CPU continues uninterrupted. After
any reset, the G bit is cleared by default and can only be set by a
software instruction. When an interrupt is recognized, the G bit is
cleared after the PC is stacked and the interrupt vector is fetched. After
the interrupt is serviced, a return from interrupt instruction is normally
executed to restore the PC to the value that was present before the
interrupt occurred. The G bit is set after a return from interrupt is
executed. Although the G bit can be set within an interrupt service
routine, “nesting” interrupts in this way should only be done when there
is a clear understanding of latency and of the arbitration mechanism.
4.2 Interrupt handling
When an interrupt is recognized, the current instruction completes its
execution. The return address (the current value in the program
counter) is pushed onto the stack and execution continues at the
address specified by the unique interrupt vector (see Table 9). This
process takes five instruction cycles. At the end of the interrupt
service routine, a RETI instruction is executed. The RETI instruction
causes the saved address to be pulled off the stack in reverse order.
The G bit is set and program execution resumes at the return address.
The ACE1101 is capable of supporting four interrupts. Three are
maskable through the G bit of the Status register and the fourth
(software interrupt) is not inhibited by the G bit (see Figure 13). (See
Table 6 for the interrupt priority sequence.) The software interrupt
instruction is executed in a manner similar to other maskable
interrupts in that the program counter registers are stacked. How-
ever, with a software interrupt, the G bit is not effected. This means,
when returning from a software interrupt, a RET instruction should
be used rather than using the RETI instruction. The RETI instruction
will set the G bit.
4.3 Addressing Modes
The ACE1101 has seven addressing modes.
In this addressing mode, a 8-bit unsigned offset value is added to
the X-pointer yielding a new effective address. This mode can be
used to address any memory location (Instruction or Data).
Table 6: Interrupt Priority Sequence
This is the “normal” addressing mode. The operand is the data
memory addressed by the X-pointer.
Priority (4 highest, 1 lowest)
ACE1101 Rev. C.8