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FDC37C669-MT View Datasheet(PDF) - SMSC -> Microchip

Part NameDescriptionManufacturer
FDC37C669-MT PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support SMSC
SMSC -> Microchip SMSC
FDC37C669-MT Datasheet PDF : 162 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
QFP/
TQFP
PIN NO.
NAME
48-51 Data Bus 0-7
53-56
44 nI/O Read
45 nI/O Write
46 Address Enable
28-34
41-43,
97
I/O Address
21,52, DMA Request
99 A, B, C
22,36,
96
nDMA
Acknowledge
A, B, C
35 Terminal Count
DESCRIPTION OF PIN FUNCTIONS
SYMBOL
BUFFER
TYPE
DESCRIPTION
HOST PROCESSOR INTERFACE
D0-D7
I/O24
The data bus connection used by the host
microprocessor to transmit data to and from
the chip. These pins are in a high-impedance
state when not in the output mode.
nIOR
I
This active low signal is issued by the host
microprocessor to indicate a read operation.
nIOW
I
This active low signal is issued by the host
microprocessor to indicate a write operation.
AEN
I
Active high Address Enable indicates DMA
operations on the host data bus. Used
internally to qualify appropriate address
decodes.
A0-A10
I
These host address bits determine the I/O
address to be accessed during nIOR and
nIOW cycles. These bits are latched internally
by the leading edge of nIOR and nIOW. All
internal address decodes use the full A0 to
A10 address bits.
DRQ_A
DRQ_B
DRQ_C
O24 This active high output is the DMA request for
byte transfers of data between the host and
the chip. This signal is cleared on the last
byte of the data transfer by the nDACK signal
going low (or by nIOR going low if nDACK was
already low as in demand mode).
nDACK_A
nDACK_B
nDACK_C
I
An active low input acknowledging the request
for a DMA transfer of data between the host
and the chip. This input enables the DMA
read or write internally.
TC
I
This signal indicates to the chip that DMA data
transfer is complete. TC is only accepted
when nDACK_x is low. In AT and PS/2 model
30 modes, TC is active high and in PS/2
mode, TC is active low.
6
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