MAIN STATUS REGISTER
Address 3F4 READ ONLY
The Main Status Register is a read-only register and
indicates the status of the disk controller. The Main
Status Register can be read at any
time. The MSR indicates when the disk controller is ready
to receive data via the Data Register. It should be read
before each byte transferring to or from the data register
except in DMA mode. NO delay is required when reading
the MSR after a data transfer.
NON CMD DRV3 DRV2 DRV1 DRV0
DMA BUSY BUSY BUSY BUSY BUSY
BIT 0 - 3 DRV x BUSY
These bits are set to 1s when a drive is in the seek
portion of a command, including implied and overlapped
seeks and recalibrates.
BIT 4 COMMAND BUSY
This bit is set to a 1 when a command is in progress.
This bit will go active after the command byte has been
accepted and goes inactive at the end of the results
phase. If there is no result phase (Seek, Recalibrate
commands), this bit is returned to a 0 after the last
BIT 5 NON-DMA
This mode is selected in the SPECIFY command and will
be set to a 1 during the execution phase of a command.
This is for polled data transfers and helps differentiate
between the data transfer phase and the reading of result
BIT 6 DIO
Indicates the direction of a data transfer once a RQM is
set. A 1 indicates a read and a 0 indicates a write is
BIT 7 RQM
Indicates that the host can transfer data if set to a 1. No
access is permitted if set to a 0.