FDC37C669FR View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37C669FR

Super I/O Floppy Disk Controller with Fast Infrared Support

SMSC -> Microchip 

DIGITAL OUTPUT REGISTER (DOR)

Address 3F2 READ/WRITE

The DOR controls the drive select and motor

enables of the disk interface outputs. It

also contains the enable for the DMA logic

and contains a software reset bit. The contents

of the DOR are unaffected by a software reset.

The DOR can be written to at any time.

RESET

COND.

7

MOT

EN3

0

6

MOT

EN2

0

5

MOT

EN1

0

4

MOT

EN0

0

3

2

1

0

DMAEN nRESET DRIVE DRIVE

SEL1 SEL0

0

0

0

0

BIT 0 and 1 DRIVE SELECT

These two bit a are binary encoded for the four

drive selects DS0-DS3, thereby allowing only

one drive to be selected at one time.

BIT 2 nRESET

A logic "0" written to this bit resets the Floppy

disk controller. This reset will remain active

until a logic "1" is written to this bit. This

software reset does not affect the DSR and CCR

registers, nor does it affect the other bits of the

DOR register. The minimum reset duration

required is 100ns, therefore toggling this bit by

consecutive writes to this register is a valid

method of issuing a software reset.

BIT 3 DMAEN

PC/AT and Model 30 Mode:

Writing this bit to logic "1" will enable the DRQ,

nDACK, TC and FINTR outputs. This bit being

a logic "0" will disable the nDACK and TC

inputs, and hold the DRQ and FINTR outputs in

a high impedance state. This bit is a logic "0"

after a reset and in these modes.

PS/2 Mode: In this mode the DRQ, nDACK, TC

and FINTR pins are always enabled. During a

reset, the DRQ, nDACK, TC, and FINTR pins

will remain enabled, but this bit will be cleared to

a logic "0".

BIT 4 MOTOR ENABLE 0

This bit controls the MTR0 disk interface output.

A logic "1" in this bit will cause the output pin to

go active.

BIT 5 MOTOR ENABLE 1

This bit controls the MTR1 disk interface output.

A logic "1" in this bit will cause the output pin to

go active.

BIT 6 MOTOR ENABLE 2

This bit controls the MTR2 disk interface output.

A logic "1" in this bit will cause the output pin to

go active.

BIT 7 MOTOR ENABLE 3

This bit controls the MTR3 disk interface output.

A logic "1" in this bit causes the output to go

active.

24

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