IMP1832 View Datasheet(PDF) - IMP, Inc
Part Name
Description
Manufacturer
IMP1832 Datasheet PDF : 7 Pages
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IMP1832
Application Information
Supply Voltage Monitor
The IMP1832 monitors the microprocessor or microcontroller
power supply and issues reset signals, both active HIGH and
active LOW, that halt processor operation whenever the power
supply voltage levels are outside a predetermined tolerance.
On power-down, once VCC falls below the reset threshold RESET
stays LOW and is guaranteed to be 0.4V or less until VCC drops
below 1.2V. The active HIGH reset signal is valid down to a VCC
level of 1.2V also.
Tolerance levels are set with the TOL pin.
RESET and RESET signals are generated at the last moment of a
valid VCC signal. On power-up, both reset signals are active for a
minimum of 250ms after the supply has returned to intolerance
level. This allows the power supply and monitored processor to
stabilize before instruction execution is allowed to begin.
Tolerance
Select
TOL = VCC
TOL = GND
Tolerance
20%
10%
TRIP Point Voltage (V)
Min Nominal Max
2.47
2.55
2.64
2.80
2.88
2.97
1832 t02.eps
Trip Point Tolerance Selection
With TOL connected to VCC, RESET and RESET become active
whenever VCC falls below 2.64V. RESET and RESET become active
when VCC falls below 2.98V if TOL is connected to ground.
After VCC has risen above the trip point set by TOL, RESET and
RESET remain active for a minimum time period of 250ms.
VCCTP(MIN)
tR
VCVCCTCPTP(MAX)
VCC
tRPU
RESET
VOH
Manual Reset Operation
Push-button switch input, PBRST, allows the user to override the
internal trip point detection circuits and issue reset signals. The
pushbutton input is debounced and is pulled HIGH through an
internal 40kΩ resistor.
When PBRST is held LOW for the minimum time tPB , both resets
become active and remain active for a minimum time period of
250ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses greater
than 20ms. No external pull-up resistor is required, since PBRST
is pulled HIGH by an internal 40kΩ resistor.
The PBRST can be driven from a TTL or CMOS logic line or short-
ed to ground with a mechanical switch.
PBRST
tPB
tPDLY
VIH
VIL
VOL
Figure 1. Timing Diagram: Power Up
RESET
1832_04.eps
VCC
VCCTP(MAX)
VCCTP
tF
VCCTP(MIN)
tRST
RESET
RESET
VOH
VOL
1832_07.eps
Figure 3. Timing Diagram: Pushbutton Reset
IMP1832
Supply
Voltage
RESET
tRPD
RESET
VOH
VOL
Figure 2. Timing Diagram: Power Down
1832_03.eps
1
PBRST
2
TD
8
VCC
7
ST
3
6
TOL RESET
4
5
GND RESET
µP
RESET
1832_05.eps
Figure 4. Application Circuit: Pushbutton Reset
4
408-432-9100/www.impweb.com
© 1999 IMP, Inc.
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