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FS6130-03 View Datasheet(PDF) - AMI Semiconductor

Part Name
Description
Manufacturer
FS6130-03
AMI
AMI Semiconductor AMI
FS6130-03 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
FS6130
VCXO Clock Generator IC
AMERICAN MICROSYSTEMS, INC.
Preliminary
May 2000
Table 7: AC Timing Specifications (VDD = 3.3V nominal)
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ f rom typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX. UNITS
Overall
Synthesis Error
Clock Output (CLKx)
Duty Cycle *
Jitter, Period (peak-peak) *
Jitter, Long Term (σy(τ )) *
Rise Time *
Fall Time *
(unless otherwise noted in Frequency Table)
Ratio of high pulse width (as measured from rising edge
to next falling edge at VDD/2) to one clock period
tj(P)
From rising edge to next rising edge at
VDD/2, CL = 10pF
tj(LT)
From 0-500µs at VDD/2, CL = 10pF
compared to ideal clock source
tr
VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF
tf
VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF
0
ppm
45
55
%
390
ps
155
ps
1.7
ns
1.7
ns
Table 8: AC Timing Specifications (VDD = 5V nominal)
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ f rom typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX. UNITS
Overall
Synthesis Error
Clock Output (CLKx)
Duty Cycle *
Jitter, Period (peak-peak) *
Jitter, Long Term (σy(τ )) *
Rise Time *
Fall Time *
(unless otherwise noted in Frequency Table)
Ratio of high pulse width (as measured from rising edge
to next falling edge at VDD/2) to one clock period
tj(P)
From rising edge to next rising edge at
VDD/2, CL = 10pF
tj(LT)
From 0-500µs at VDD/2, CL = 10pF
compared to ideal clock source
tr
VDD = 5V; VO = 0.5V to 4.5V; CL = 10pF
tf
VDD = 5V; VO = 4.5V to 0.5V; CL = 10pF
0
ppm
45
55
%
390
ps
155
ps
1.0
ns
1.0
ns
6
ISO9001
5.1.00
 

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