11525-801 View Datasheet(PDF) - AMI Semiconductor
Part Name
Description
Manufacturer
11525-801 Datasheet PDF : 26 Pages
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April 1999
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN
(FS6251)
PIN
(FS6252)
TYPE
NAME
DESCRIPTION
22, 23
35, 36, 39, 40
30
44, 45
8, 10, 11, 13,
14, 16, 17
7
31
29
1, 2, 47
26, 27
25
28
19, 33
46
37, 41
9, 15
48
21
20, 32
43
34, 38
6, 12, 18
3
24
4
5
42
-
23, 24
18
-
5, 7, 8, 9
4
19
17
26
16
15
-
13, 21
-
25
9, 12
27
-
14, 20
-
22
3, 12
28
-
1
2
-
DO
48M_0:1
Two 48MHz clock outputs for Universal Serial Bus (USB) timing
DO
CPU_0:3
Four low-skew (<175ps @ 1.25V) 2.5V to 3.3V CPU clock outputs for host
frequencies. (Two copies of the CPU clock are available in FS6252 version)
DIU
CPU_STOP#
CPU_0:3 clock output enable. Asynchronous, active-low disable stops all
CPU clocks in the low state.
DO
APIC_0:1
Two buffered low-skew (<175ps @ 1.25V) 2.5V/3.3V outputs of the
14.318MHz reference clock for APIC bus timing
Seven low-skew (<250ps @ 1.5V) 3.3V PCI clock outputs. PCI clocks are
DO
PCI_1:7
synchronous with CPU clocks but lag the CPU clocks by 1ns to 4ns. (Four
copies of the PCI clock are available in FS6252 version)
DO
PCI_F
One free-running 3.3V PCI clock output.
DIU
PCI_STOP#
PCI_1:7 clock output enable. Asynchronous, active-low disable stops all PCI
clocks in the low state.
DIU
PWR_DWN#
Asynchronous active-low power-down signal shuts down oscillator, all PLLs,
puts all clocks in low state. Clock re-enable latency of ≤ 3ms.
DO
REF_0:2
Three buffered outputs of the 14.318MHz reference clock. (One copy of the
reference clock is available in FS6252 version)
DIU
SEL_0:1
Two frequency select inputs (Both SEL pins are tied together in FS6252
version)
DI
SEL_100/66#
Selects 100MHz or 66MHz CPU clock frequency (pull-up/pull-down must be
provided externally)
DIU
SS_EN#
Spread spectrum enable. Active-low enable turns on the spread spectrum
feature; a logic-high turns off the spread spectrum modulation.
P
VDD
3.3V ± 10%
P
VDD_A
Power supply for 2.5V APIC_0:1 clock outputs
P
VDD_C
Power supply for 2.5V CPU_0:3 clock outputs
P
VDD_P
Power supply for 3.3V PCI_1:7 and PCI_F clock outputs
P
VDD_R
Power supply for 3.3V REF_0:2 clock outputs
P
VDD_U
Power supply for 3.3V 48M_0:1 clock outputs
P
VSS
Ground
P
VSS_A
Ground for APIC_0:1 clock outputs
P
VSS_C
Ground for CPU_0:3 clock outputs
P
VSS_P
Ground for PCI_1:7 and PCI_F clock outputs
P
VSS_R
Ground for REF_0:2 clock outputs
P
VSS_U
Ground for 48M_0:1 clock outputs
AI
XIN
14.318MHz crystal oscillator feedback
AO
XOUT
14.318MHz crystal oscillator drive
-
(reserved) reserved
4.5.99
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2
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