11525-801 View Datasheet(PDF) - AMI Semiconductor
Part Name
Description
Manufacturer
11525-801 Datasheet PDF : 26 Pages
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April 1999
Table 9: AC Timing Specifications, continued
Unless otherwise stated, all power supplies = 3.3V ± %, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal char-
acterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
100MHz
66.67MHz
UNITS
MIN. TYP. MAX. MIN. TYP. MAX.
REF_0:2, 48M_0:1 Clock Outputs (3.3V Type 3 Clock Buffer)
Duty Cycle *
Jitter, Long Term (σy(τ)) *
Jitter, Period (peak-peak) *
Rise Time *
Fall Time *
Ratio of high pulse width, as measured
from rising edge to next falling edge at
45
1.5V, to one clock period
55
45
55
%
On rising edges 500µs apart at 1.5V
tj(LT)
relative to an ideal clock, CL=20pF, all
51
PLLs active
54
ps
tj(∆P)
From rising edge to next rising edge at
1.5V, CL=20pF, all PLLs active
199
252
ps
tr min
tr max
Measured @ 0.4V – 2.4V; CL = 10pF
Measured @ 0.4V – 2.4V; CL = 20pF
1.0 1.3
1.0 1.3
ns
2.0 4.0
2.0 4.0
tf min
tf max
Measured @ 2.4V – 0.4V; CL = 10pF
Measured @ 2.4V – 0.4V; CL = 20pF
1.0 1.6
1.0 1.6
ns
2.0 4.0
2.0 4.0
PCI_1:7, PCI_F Clock Outputs (3.3V Type 5 Clock Buffer)
Duty Cycle *
Jitter, Long Term (σy(τ)) *
Jitter, Period (peak-peak) *
Rise Time *
Fall Time *
Enable Delay *
Disable Delay *
Ratio of high pulse width, as measured
from rising edge to next falling edge at
45
1.5V, to one clock period
55
45
55
%
tj(LT)
On rising edges 500µs apart at 1.5V
relative to an ideal clock, CL=30pF, all
PLLs active
293
263
ps
tj(∆P)
From rising edge to next rising edge at
1.5V, CL=30pF, all PLLs active
148 500
146 500
ps
tr min
tr max
Measured @ 0.4V – 2.4V; CL = 15pF
Measured @ 0.4V – 2.4V; CL = 30pF
0.5 1.0
0.5 1.0
ns
1.4 2.0
1.4 2.0
tf min
tf max
Measured @ 2.4V – 0.4V; CL = 15pF
Measured @ 2.4V – 0.4V; CL = 30pF
0.5 1.1
0.5 1.1
ns
1.5 2.0
1.5 2.0
tDLH
via PCI_STOP#
30
60
30
60
ns
tDHL
via PCI_STOP#
15
45
15
45
ns
4.5.99
,62
12
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