AD8042(2006) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD8042 Datasheet PDF : 16 Pages
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The circuit was tested with a 1 MHz input signal and clocked at
10 MHz. An FFT response of the digital output is shown in
Figure 42.
Pin 5 is biased at 2.5 V by the voltage divider and bypassed.
This biases each output at 2.5 V. VIN is ac-coupled such that
VIN going positive makes VINA go positive and VINB go in
the negative direction. The opposite happens for a negative
going VIN.
1
9
2
3
7
6
5
8
4
FUND FRQ 1000977
SMPL FRQ 10000000
HARMONICS (dBc)
THD –82.00
SNR 71.13
SINAD 70.79
SFDR –86.74
2ND –88.34
3RD –86.74
4TH –99.26
5TH –90.67
6TH –99.47
7TH –91.16
8TH –97.25
9TH –91.61
Figure 42. FFT of the AD9220 Output When Driven by the AD8042
HDSL Line Driver
High-bit-rate digital subscriber line (HDSL) is a popular means
of providing data communication at DS1 rates (1.544 Mbps)
over moderate distances via conventional telephone twisted pair
wires. In these systems, the transceiver at the customer’s end is
powered sometimes via the twisted pair from a power source at
the central office. Sometimes, it is required to raise the dc
voltage of the power source to compensate for IR drops in
long lines or lines with narrow gauge wires.
Because of this, it is highly desirable to keep the power
consumption of the customer’s transceiver as low as possible.
One means to realize significant power savings is to run the
transceiver from a ±5 V supply instead of the more
conventional ±12 V.
The high output swing and current drive capability of the
AD8042 make it ideally suited to this application. Figure 43
shows a circuit for the analog portion of an HDSL transceiver
using the AD8042 as the line driver.
AD8042
232Ω
VIN
0.001µF
2kΩ
3kΩ
6
5
2kΩ
2
3
7
1/2
AD8042
3kΩ
1
1/2
AD8042
912Ω
0.0027µF
2kΩ
0.001µF
ATT
2718AF
93DJ39
1
4
10
5
VOUT
2
7
9
6
34Ω
2kΩ 2kΩ
2
2kΩ
3
1 249Ω
1/4
2kΩ AD8044
VREC
Figure 43. HDSL Line Driver
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8042 requires
careful attention to board layout and component selection.
Proper RF design techniques and low-pass parasitic component
selection are necessary.
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance path. The ground plane should be removed from
the area near the input pins to reduce the stray capacitance.
Chip capacitors should be used for the supply bypassing. One
end should be connected to the ground plane and the other
within ⅛-inch of each power pin. An additional large (0.47 μF
to 10 μF) tantalum electrolytic capacitor should be connected in
parallel but not necessarily so close to supply current for fast,
large signal changes at the output.
The feedback resistor should be located close to the inverting
input pin to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the
inverting input significantly affect high speed performance.
Stripline design techniques should be used for long signal
traces (greater than approximately one inch). These should be
designed with a characteristic impedance of 50 Ω or 75 Ω and
be properly terminated at each end.
Rev. D | Page 15 of 16
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