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AD8042-2006 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD8042(2006) Dual 160 MHz Rail-to-Rail Amplifier ADI
Analog Devices ADI
AD8042 Datasheet PDF : 16 Pages
First Prev 11 12 13 14 15 16
AD8042
OVERDRIVE RECOVERY
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this
overdrive condition. As shown in Figure 35, the AD8042
recovers within 30 ns from negative overdrive and within 25 ns
from positive overdrive.
5.0V
2.5V
0V
1V
G = +2
VS = 5V
VIN = 5V p-p
RL = 1kTO 2.5V
Figure 35. Overdrive Recovery
50ns
CIRCUIT DESCRIPTION
The AD8042 is fabricated on Analog Devices proprietary eXtra-
Fast Complementary Bipolar (XFCB) process, which enables
the construction of PNP and NPN transistors with similar fTs in
the 2 GHz to 4 GHz region. The process is dielectrically isolated
to eliminate the parasitic and latch-up problems caused by
junction isolation. These features allow the construction of high
frequency, low distortion amplifiers with low supply currents.
This design uses a differential output input stage to maximize
bandwidth and headroom (see Figure 36). The smaller signal
swings required on the first stage outputs (nodes S1P, S1N)
reduce the effect of nonlinear currents due to junction
capacitances and improve the distortion performance. With this
design, harmonic distortion of better than −77 dB @ 1 MHz
into 100 Ω with VOUT = 2 V p-p (gain = +2) on a single 5 V
supply is achieved.
VCC
VINP
VINN
I1
R26
Q4
I10
R39
Q5
R15 R2
Q13 Q17
Q40
VEE
I2 I3 Q25
Q50
I9
Q36
Q51 Q39
I5
Q23 VEE
Q22
R23 R27
Q7
Q31
Q21 Q27
C3
VOUT
SIP
SIN
C9
Q2
Q11
Q3
Q24
C7
VEE
R5
R21 R3
I7
Q8
Q47
I8
VCC
Figure 36. Simplified Schematic
The AD8042’s rail-to-rail output range is provided by a
complementary common-emitter output stage. High output
drive capability is provided by injecting all output stage
predriver currents directly into the bases of the output devices
Q8 and Q36. Biasing of Q8 and Q36 is accomplished by I8 and
I5, along with a common-mode feedback loop (not shown).
This circuit topology allows the AD8042 to drive 40 mA of
output current with the outputs within 0.5 V of the supply rails.
On the input side, the device can handle voltages from 0.2 V
below the negative rail to within 1.2 V of the positive rail.
Exceeding these values does not cause phase reversal; however,
the input ESD devices do begin to conduct if the input voltages
exceed the rails by greater than 0.5 V.
DRIVING CAPACITIVE LOADS
The capacitive load drive of the AD8042 can be increased by
adding a low valued resistor in series with the load. Figure 37
shows the effects of a series resistor on capacitive drive for
varying voltage gains. As the closed-loop gain is increased, the
larger phase margin allows for larger capacitive loads with less
overshoot. Adding a series resistor with lower closed-loop gains
accomplishes the same effect. For large capacitive loads, the
frequency response of the amplifier is dominated by the roll-off
of the series resistor and capacitive load.
1000
VS = 5V
200mV STEP WITH 90% OVERSHOOT
RS
CL
RS = 5
RS = 0
100
RS = 20
10
1
2
3
4
5
CLOSED-LOOP GAIN (V/V)
Figure 37. Capacitive Load Drive vs. Closed-Loop Gain
Rev. D | Page 12 of 16
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