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ISPLSI2128VL-135LT100 View Datasheet(PDF) - Lattice Semiconductor

Part NameDescriptionManufacturer
ISPLSI2128VL-135LT100 2.5V In-System Programmable SuperFAST™ High Density PLD Lattice
Lattice Semiconductor Lattice
ISPLSI2128VL-135LT100 Datasheet PDF : 17 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Specifications ispLSI 2128VL
ispLSI 2128VL Timing Model
I/O Cell
GRP
Ded. In
I/O Pin
(Input)
#21
I/O Delay
#20
GRP
#22
#45
Reset
GLB
Feedback
Comb 4 PT Bypass #23
Reg 4 PT Bypass
#24
GLB Reg Bypass
#28
20 PT
XOR Delays
#25, 26, 27
GLB Reg
Delay
D
Q
RST
#29, 30,
31, 32
ORP
I/O Cell
ORP Bypass
#37
ORP
Delay
#36
#38,
39
I/O Pin
(Output)
Y0,1,2
GOE 0
#43, 44
#42
Control RE
PTs OE
#33, 34, CK
35
Derivations of tsu, th and tco from the Product Term Clock
tsu
= Logic + Reg su - Clock (min)
= (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
= (#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
4.0ns = (0.4 + 1.1 + 4.0) + (1.2) - (0.4 + 1.1 + 1.2)
th
= Clock (max) + Reg h - Logic
= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
= (#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
3.0ns = (0.4 + 1.1 + 4.2) + (2.8) - (0.4 + 1.1 + 4.0)
tco
= Clock (max) + Reg co + Output
= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #22 + #35) + (#31) + (#36 + #38)
9.0ns = (0.4 + 1.1 + 4.2) + (0.3) + (1.4 + 1.6)
Note: Calculations are based upon timing specifications for the ispLSI 2128VL-150L.
Table 2-0042/2128VL
#40, 41
0491/2032
7
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