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ISPLSI2128VL-135LT100 View Datasheet(PDF) - Lattice Semiconductor

Part NameDescriptionManufacturer
ISPLSI2128VL-135LT100 2.5V In-System Programmable SuperFAST™ High Density PLD Lattice
Lattice Semiconductor Lattice
ISPLSI2128VL-135LT100 Datasheet PDF : 17 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Specifications ispLSI 2128VL
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER #2
DESCRIPTION
Inputs
tio
20 Input Buffer Delay
tdin
21 Dedicated Input Delay
GRP
tgrp
22 GRP Delay
GLB
t4ptbpc
t4ptbpr
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
t1ptxor
t20ptxor
txoradj
tgbp
25 1 Product Term/XOR Path Delay
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay 3
28 GLB Register Bypass Delay
tgsu
tgh
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
tgco
31 GLB Register Clock to Output Delay
tgro
tptre
tptoe
tptck
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
ORP
torp
torpbp
36 ORP Delay
37 ORP Bypass Delay
Outputs
tob
tsl
toen
todis
tgoe
38 Output Buffer Delay
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
Clocks
tgy0
tgy1/2
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
Global Reset
tgr
45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
-150
-135
-100
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
0.4 1.0 0.9 ns
1.5 2.2 2.7 ns
1.1 1.2 1.8 ns
2.5 3.2 5.2 ns
3.0 3.2 4.7 ns
4.0 4.2 6.2 ns
4.0 4.2 6.2 ns
4.0 4.2 6.2 ns
0.0 0.5 1.0 ns
1.2 1.7 1.7 ns
2.8 3.3 4.8 ns
0.3 0.3 0.3 ns
0.6 1.1 4.3 ns
4.9 6.6 8.9 ns
5.0 5.8 7.4 ns
1.2 4.2 2.1 4.5 2.8 4.8 ns
1.4 1.5 1.5 ns
0.4 0.5 0.5 ns
1.6 1.6 1.6 ns
2.0 2.0 2.0 ns
3.5 4.0 4.9 ns
3.5 4.0 4.9 ns
2.5 3.0 4.1 ns
1.7 1.7 2.1 2.1 2.6 2.6 ns
1.9 1.9 2.3 2.3 2.8 2.8 ns
3.4
4.8
7.1 ns
Table 2-0036/2128VL
6
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