ISPLSI2128VL-135LB208I Datasheet PDF

ISPLSI2128VL-135LB208I View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

ISPLSI2128VL-135LB208I

2.5V In-System Programmable SuperFAST™ High Density PLD

Lattice Semiconductor

ISPLSI2128VL-135LB208I Datasheet PDF : 17 Pages

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Specifications ispLSI 2128VL

Functional Block Diagram

Figure 1. ispLSI 2128VL Functional Block Diagram (128-I/O and 64-I/O Versions)

RESET

GOE 0

GOE 1

Megablock

Generic Logic

Blocks (GLBs)

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

TDI/IN 0

TMS/IN 1

BSCAN

Global

Routing

Pool

(GRP)

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

IN 5

IN 4

I/O 95

I/O 94

I/O 93

I/O 92

I/O 91

I/O 90

I/O 89

I/O 88

I/O 87

I/O 86

I/O 85

I/O 84

I/O 83

I/O 82

I/O 81

I/O 80

I/O 79

I/O 78

I/O 77

I/O 76

I/O 75

I/O 74

I/O 73

I/O 72

I/O 71

I/O 70

I/O 69

I/O 68

I/O 67

I/O 66

I/O 65

I/O 64

0139B/2128VL

RESET

GOE 0

GOE 1

Megablock

Generic Logic

Blocks (GLBs)

I/O 0

I/O 1

I/O 2

I/O 3

Input Bus

Output Routing Pool (ORP)

IN 5*

IN 4*

I/O 47

I/O 46

I/O 45

I/O 44

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

Global

Routing

Pool

(GRP)

I/O 43

I/O 42

I/O 41

I/O 40

I/O 39

I/O 38

I/O 37

I/O 36

I/O 12

I/O 13

I/O 14

I/O 15

TDI/IN 0

TMS/IN 1

I/O 35

I/O 34

I/O 33

I/O 32

BSCAN

Output Routing Pool (ORP)

Input Bus

0139B/2128VL.64IO

*Not available on 84-PLCC Device

The 128-I/O 2128VL contains 128 I/O cells, while the 64-

I/O version contains 64 I/O cells. Each I/O cell is directly

connected to an I/O pin and can be individually pro-

grammed to be a combinatorial input, output or

bi-directional I/O pin with 3-state control, and the output

drivers can source 4mA or sink 8mA. Each output can be

programmed independently for fast or slow output slew

rate to minimize overall output switching noise. Device

pins can be safely driven to 3.3V signal levels to support

mixed-voltage systems.

Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and

two or one ORPs are connected together to make a

Megablock (see Figure 1). The outputs of the eight GLBs

are connected to a set of 32 or 16 universal I/O cells by

the two or one ORPs. Each ispLSI 2128VL device con-

tains four Megablocks.

GLB basis. The asynchronous or Product Term clock can

be generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the

outputs of the ispLSI 2128VL are individually program-

mable, either as a standard totem-pole output or an

open-drain output. The totem-pole output drives the

specified Voh and Vol levels, whereas the open-drain

output drives only the specified Vol. The Voh level on the

open-drain output depends on the external loading and

pull-up. This output configuration is controlled by a pro-

grammable fuse. The default configuration is a totem-pole

configuration. The open-drain/totem-pole option is se-

lectable through the ispDesignEXPERT software tools.

The GRP has as its inputs, the outputs from all of the

GLBs and all of the inputs from the bi-directional I/O cells.

All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 2128VL device are selected using

the dedicated clock pins. Three dedicated clock pins (Y0,

Y1, Y2) or an asynchronous clock can be selected on a

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