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M12L16161A(2Q) View Datasheet(PDF) - Unspecified

Part Name
Description
Manufacturer
M12L16161A(2Q)
ETC
Unspecified ETC
M12L16161A(2Q) Datasheet PDF : 28 Pages
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ESMT
M12L16161A (2Q)
Operation Temperature Condition -40°C~85°C
AC OPERATING TEST CONDITIONS (VDD=3.3V ± 0.3V, TA= -40 to 85 °C )
Parameter
Value
Unit
Input levels (Vih/Vil)
2.4 / 0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr / tf = 1 / 1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig.2
Output
870
3.3V
1200
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
30 pF
Output
Z0=50
Vtt =1.4V
50 Ω
30 pF
(Fig.1) DC Output Load circuit
(Fig.2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
-5
-7
Unit
Note
Row active to row active delay
tRRD(min)
10
14
ns
1
RAS to CAS delay
tRCD(min)
15
21
ns
1
Row precharge time
tRP(min)
Row active time
tRAS(min)
tRAS(max)
Row cycle time
@ Operating
@ Auto refresh
tRC(min)
tRFC(min)
Last data in to new col. Address delay
tCDL(min)
Last data in to row precharge
tRDL(min)
Last data in to burst stop
tBDL(min)
Col. Address to col. Address delay
tCCD(min)
Number of valid output data
CAS Latency=3
CAS Latency=2
15
21
30
42
100
45
63
55
63
1
2
1
1
2
1
ns
1
ns
1
us
ns
1
ns
1, 5
CLK
2
CLK
2
CLK
2
CLK
3
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
5. A new command may be given tRFC after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2012
Revision : 1.0
5/28
 

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