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ST6201BD3 Просмотр технического описания (PDF) - STMicroelectronics

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ST6201BD3 8-bit MCUs with A/D converter,two timers, oscillator safeguard & safe reset ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST6201BD3 Datasheet PDF : 100 Pages
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ST6200C ST6201C ST6203C
5.11 REGISTER DESCRIPTION
INTERRUPT OPTION REGISTER (IOR)
Address: 0C8h — Write Only
Reset status: 00h
7
0
- LES ESB GEN -
-
-
-
Caution: This register is write-only and cannot be
accessed by single-bit operations (SET, RES,
DEC,...).
Bit 7 =Reserved, must be cleared.
1: Low level sensitive mode is selected for inter-
rupt vector #1
Bit 5 = ESB Edge Selection bit.
0: Falling edge mode on interrupt vector #2
1: Rising edge mode on interrupt vector #2
Bit 4 = GEN Global Enable Interrupt.
0: Disable all maskable interrupts
1: Enable all maskable interrupts
Note: When the GEN bit is cleared, the NMI inter-
rupt is active but cannot be used to exit from STOP
or WAIT modes.
Bit 6 = LES Level/Edge Selection bit.
0: Falling edge sensitive mode is selected for inter-
rupt vector #1
Bits 3:0 = Reserved, must be cleared.
Table 7. Interrupt Mapping
Vector
number
Vector #0
Source
Block
RESET
NMI
Description
Reset
Non Maskable Interrupt
Register
Label
N/A
N/A
NOT USED
Vector #1
Vector #2
Vector #3
Vector #4
Port A
Port B
TIMER
ADC *
Ext. Interrupt Port A
Ext. Interrupt Port B
Timer underflow
End Of Conversion
N/A
N/A
TSCR
ADCR
* Depending on device. See device summary on page 1.
Flag
N/A
N/A
N/A
N/A
TMZ
EOC
Exit
from
STOP
yes
yes
yes
yes
yes
no
Vector
Address
FFEh-FFFh
FFCh-FFDh
FFAh-FFBh
FF8h-FF9h
FF6h-FF7h
FF4h-FF5h
FF2h-FF3h
FF0h-FF1h
Priority
Order
Highest
Priority
Lowest
Priority
30/100
1
Doc ID 4563 Rev 5
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