LPC920F View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
LPC920F Datasheet PDF : 45 Pages
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Philips Semiconductors
P89LPC920/921/922
8-bit microcontrollers with two-clock 80C51 core
9397 750 12285
Product data
Flash programming and erasing: There are three methods of erasing or
programming of the Flash memory that may be used. First, the Flash may be
programmed or erased in the end-user application by calling low-level routines
through a common entry point. Second, the on-chip ISP boot loader may be invoked.
This ISP boot loader will, in turn, call low-level routines through the same common
entry point that can be used by the end-user application. Third, the Flash may be
programmed or erased using the parallel method by using a commercially available
EPROM programmer which supports this device. This device does not provide for
direct verification of code memory contents. Instead this device provides a 32-bit
CRC result on either a sector or the entire 4 kB/8 kB of user code space.
Boot ROM: When the microcontroller programs its own Flash memory, all of the
low-level details are handled by code that is contained in a Boot ROM that is separate
from the Flash memory. A user program simply calls the common entry point in the
Boot ROM with appropriate parameters to accomplish the desired operation. The
Boot ROM include operations such as erase sector, erase page, program page, CRC,
program security bit, etc. The Boot ROM occupies the program memory space at the
top of the address space from FF00 to FFFF hex, thereby not conflicting with the user
program memory space.
Power-on reset code execution: The P89LPC920/921/922 contains two special
Flash elements: the Boot Vector and the Boot Status Bit. Following reset, the
P89LPC920/921/922 examines the contents of the Boot Status Bit. If the Boot Status
Bit is set to zero, power-up execution starts at location 0000H, which is the normal
start address of the user’s application code. When the Boot Status Bit is set to a one,
the contents of the Boot Vector is used as the high byte of the execution address and
the low byte is set to 00H. The factory default setting is 1FH for the P89LPC922 and
corresponds to the address 1F00H for the default ISP boot loader. The factory default
setting is 0FH for the P89LPC921 and corresponds to the address 0F00H for the
default ISP boot loader. The factory default setting for the LPC920 is 07H and
corresponds to the address 0700H. This boot loader is pre-programmed at the factory
into this address space and can be erased by the user. Users who wish to use this
loader should take precautions to avoid erasing the 1 kB sector from
1C00H to 1FFFH in the P89LPC922 or the 1 kB sector from 0C00H to 0FFFH in
the P89LPC921, or the 1 kB sector from 0400H to 07FFH in the P89LPC920.
Instead, the page erase function can be used to erase the eight 64-byte pages
which comprise the lower 512 bytes of the sector. A custom boot loader can be
written with the Boot Vector set to the custom boot loader, if desired.
Hardware activation of the boot loader: The boot loader can also be executed by
forcing the device into ISP mode during a power-on sequence (see the
P89LPC920/921/922 User’s Manual for specific information). This has the same
effect as having a non-zero Boot Status Bit. This allows an application to be built that
will normally execute user code but can be manually forced into ISP operation. If the
factory default setting for the Boot Vector is changed, it will no longer point to the
factory pre-programmed ISP boot loader code. If this happens, the only way it is
possible to change the contents of the Boot Vector is through the parallel
programming method, provided that the end user application does not contain a
customized loader that provides for erasing and reprogramming of the Boot Vector
and Boot Status Bit. After programming the Flash, the Boot Status Bit should be
programmed to zero in order to allow execution of the user’s application code
beginning at address 0000H.
Rev. 06 — 21 November 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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