GT-6816
DMA3 enable read image
DMA3 is defined as the transfer between M2 and PC interface (ECP, EPP,
or USB).
When this bit is set to ‘1’, the incoming DMA3 transfer indicates the
transfer of image data to PC interface. The image valid data byte count
2
1’b0
will decrement by one automatically when DMA3 is a read transfer and
this bit is set to one. If this bit is cleared to ‘0’, the request for read/write
M2 by PC interface is just the memory access.
If the last line scanning is present, this bit will also be cleared
automatically when DMA2 is completed.
DMA2 enable
0 = DMA2 is disable
1 = DMA2 is enable
DMA2 is defined as the transfer from sensor input via AFE to M2.
When each line scan is complete, DMA2 event occurs and DMA2 enable
1
1’b0 bit is cleared automatically.
The address is started from the current M2 starting address and
incremented automatically. CPU can poll this bit to determine the line
scan is end or not. If overrun occurs, i.e., the image buffer is not enough to
store the incoming image data, this bit will be cleared and disable the
DMA2 transfer. In this condition, interrupt will be generated.
DMA1 enable
DMA1 is defined as the transfer from M2 to M1. The purpose of DMA1 is
to download the updated program code to M1. The updated program code
0
1’b0 must be stored in M2 before DMA1 is active.
When this bit is set to ‘1’, DMA1 is active. CPU will be halted and
transfer data from M2 to M1. This bit will be clear automatically when
DMA1 transfer is done.
DMA1 transfer bytes Count high byte register
CPU Read/Write
Address: FF81H
Bit Reset Description
7:0 8’b0 DMA1 transfer byte count high byte
DMA1 transfer bytes count low byte register
CPU Read/Write
Address: FF82H
Bit Reset Description
30