GT-6816
AFE CDSR0 control signal rising phase
CPU Read/Write
Address: FF2AH
Bit Reset Description
7
1’b0 Reserved
CDSR0 enable
6
1’b0 0 = CDSR0 output disable
1 = CDSR0 output enable
5:0 6’b0 Define rising phase referenced to 6-bits pixel counter
AFE CDSR0 control signal falling phase
CPU Read/Write
Address: FF2BH
Bit Reset Description
7:6 2’b0 Reserved
5:0 6’b0 Define falling phase referenced to 6-bits pixel counter
AFE CDSR1 control signal rising phase
CPU Read/Write
Address: FF2CH
Bit Reset Description
7
1’b0 Reserved
CDSR1 enable
6
1’b0 0 = CDSR1 output disable
1 = CDSR1 output enable
5:0 6’b0 Define rising phase referenced to 6-bits pixel counter
AFE CDSR1 control signal falling phase
CPU Read/Write
Address: FF2DH
Bit Reset Description
7:6 2’b0 Reserved
5:0 6’b0 Define falling phase referenced to 6-bits pixel counter
AFE CDSR2 control signal rising phase
CPU Read/Write
Address: FF2EH
Bit Reset Description
7
1’b0 Reserved
21